Abstract: A serial battery charger including a number of serially connected battery charging sections in which the battery charging section is characterized by a first and second parallelly connected branches. The first branch includes terminals for connecting to the battery to be charged and a current blocking device and the second branch includes a by-passing switch which shunts across the terminals of the first branch when activated. The blocking device in the first branch prevents adverse reverse current flow from the battery to the charger when there is no power supply and also functions as a current block to prevent adverse flow of current from the battery into the shunting by-passing switch when the power supply to the charging section is in operation. This invention provides a simple solution to fulfil the conflicting requirements of an intelligent serial battery charger.

Abstract: A serial battery charger including a number of serially connected battery charging sections in which the battery charging section is characterized by a first and second parallelly connected branches. The first branch includes terminals for connecting to the battery to be charged and a current blocking device and the second branch includes a by-passing switch which shunts across the terminals of the first branch when activated. The blocking device in the first branch prevents adverse reverse current flow from the battery to the charger when there is no power supply and also functions as a current block to prevent adverse flow of current from the battery into the shunting by-passing switch when the power supply to the charging section is in operation. This invention provides a simple solution to fulfil the conflicting requirements of an intelligent serial battery charger.

Abstract: A processor is provided for transforming N.times.N discrete cosine transform (DCT) coefficients F.sub.uv inputted from a run-length-code 5 (RLC) decoder and arranged in an input order into an image data f.sub.jk in an integrated circuit through a 2-D inverse discrete cosine transform (IDCT) procedure wherein subscripts u and v of DCT coefficients F.sub.uv are input frequency indices respectively having least significant bits (LSB) u.sub.0 and v.sub.0 having an exclusive-OR (XOR) and subscripts j and k of image data f.sub.jk are spatial indices generated by the integrated circuit, which comprises a cosine pre-multiplier array for computing cosine-weighted DCT coefficients, a principal subkernel mapper utilizing the cosine-weighted DCT coefficients by first referring to the indices u and v for forming a principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv, an N.times.N accumulating matrix operating with the principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.