Patents by Inventor Long Cheng Koh
Long Cheng Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11906798Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.Type: GrantFiled: August 23, 2021Date of Patent: February 20, 2024Assignee: POET Technologies, Inc.Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
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Patent number: 11725942Abstract: A photonic integrated chip is configured as a transmitter-receiver chip. The photonic integrated chip includes a light emitter, a light detector, a multi-mode interference coupler, and a mode-filed adapter. The light emitted by the light emitter is guided to a core layer formed below the multi-mode interference coupler, and further to the mode-filed adapter for transmission of light to an optical fiber coupled with the photonic integrated chip. Similarly, light received by the mode-filed adapter from the optical fiber propagates to the core layer, and is guided by the multi-mode interference coupler into the light detector. The photonic integrated chip is utilized to realize a single-unit transmitter-receiver module for a fiber optic gyroscope circuit based on monolithic integration of photonics components via wafer fabrication on a substrate. The photonic integrated chip has a low fabrication cost, low size, and is robust.Type: GrantFiled: December 16, 2021Date of Patent: August 15, 2023Assignee: DENSELIGHT SEMICONDUCTORS PTE LTDInventors: Yee Loy Lam, Ter Hoe Loh, Kamal Kader, Long Cheng Koh
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Publication number: 20220329045Abstract: A laser module includes a gain chip, temperature sensors, a case, and a thermoelectric cooler (TEC). The gain chip emits a laser beam. One of the temperature sensors measures a first temperature of the gain chip and is encompassed by the gain chip. The other temperature sensor is adhered to the case and measures a second temperature. The TEC tunes the laser beam emitted by the gain chip to a desired wavelength by varying the first temperature of the gain chip through a set of third temperatures for various values of the second temperature. The set of third temperatures is selected from various values of the first temperature such that the laser beam emitted at the set of third temperatures is mode-hop free.Type: ApplicationFiled: March 24, 2022Publication date: October 13, 2022Applicant: DENSELIGHT SEMICONDUCTORS PTE LTDInventors: Kamal Kader, Long Cheng Koh, Andy Piper, Yee Loy Lam
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Publication number: 20220283271Abstract: A beam scanning system includes a light source, an optical switch, a set of spectral dispersive elements, and a set of contour dispersive arrays. The light source emits a beam of light that is received by at least one of the optical switch or a spectral dispersive element. The optical switch emits the received beam of light from an output port that is selected based on a control signal. The spectral dispersive element receives the beam of light from the optical switch. The spectral dispersive element disperses the beam of light to scan a desired target area. One of the contour dispersive arrays receives the dispersed beam of light from the spectral dispersive array and refracts the dispersed beam of light into an array of light beams that scan a desired target area.Type: ApplicationFiled: March 1, 2022Publication date: September 8, 2022Inventors: Long Cheng Koh, Yee Loy Lam
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Publication number: 20220231477Abstract: An optoelectronic device includes a semiconductor die that includes a substrate layer, a laser diode, first and second conducting pads, a cathode pad, an anode pad, and a passivation layer. The laser diode and the conducting pads are formed on the substrate layer. The formation of the conducting pads directly on the substrate layer offers an increased area for heat dissipation. The cathode pad is formed on the first conducting pad whereas the anode pad is formed above the second conducting pad. The passivation layer is formed above the laser diode. The attachment of the semiconductor die to a submount of the optoelectronic device occurs by way of the cathode pad and the anode pad. After the attachment, a free space is created directly between the passivation layer and the submount to reduce the impact of solder bonding stress on the laser diode.Type: ApplicationFiled: January 19, 2022Publication date: July 21, 2022Applicant: DENSELIGHT SEMICONDUCTORS PTE LTDInventors: Yee Loy Lam, Hon Yuen Aaron Sim, Lay Cheng Choo, Long Cheng Koh
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Publication number: 20220187074Abstract: A photonic integrated chip is configured as a transmitter-receiver chip. The photonic integrated chip includes a light emitter, a light detector, a multi-mode interference coupler, and a mode-filed adapter. The light emitted by the light emitter is guided to a core layer formed below the multi-mode interference coupler, and further to the mode-filed adapter for transmission of light to an optical fiber coupled with the photonic integrated chip. Similarly, light received by the mode-filed adapter from the optical fiber propagates to the core layer, and is guided by the multi-mode interference coupler into the light detector. The photonic integrated chip is utilized to realize a single-unit transmitter-receiver module for a fiber optic gyroscope circuit based on monolithic integration of photonics components via wafer fabrication on a substrate. The photonic integrated chip has a low fabrication cost, low size, and is robust.Type: ApplicationFiled: December 16, 2021Publication date: June 16, 2022Applicant: DENSELIGHT SEMICONDUCTORS PTE LTDInventors: Yee Loy Lam, Ter Hoe Loh, Kamal Kader, Long Cheng Koh
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Publication number: 20220019021Abstract: A photonic integrated circuit (PIC) includes various mode field adapters (MFAs), a waveguide, and various contact pads. All the MFAs are on a same facet of the PIC. One MFA of the PIC outputs a first optical signal that is an amplified version of a second optical signal. The waveguide is divided into two waveguide arms and a bend portion to join the two waveguide arms. The waveguide extends between the MFAs such that the second optical signal propagates through the waveguide. Further, each waveguide arm is formed between the contact pads. The second optical signal propagating through the waveguide is amplified based on a current that is injected in the PIC by way of the contact pads.Type: ApplicationFiled: July 12, 2021Publication date: January 20, 2022Applicant: DenseLight Semiconductors Pte LtdInventors: Andy Piper, Ter Hoe Loh, Hon Yuen Aaron Sim, Long Cheng Koh, Yuen Chuen Chan, Yee Loy Lam
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Publication number: 20210389532Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.Type: ApplicationFiled: August 23, 2021Publication date: December 16, 2021Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
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Patent number: 11099338Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.Type: GrantFiled: January 25, 2019Date of Patent: August 24, 2021Assignee: POET Technologies, Inc.Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
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Publication number: 20190361180Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.Type: ApplicationFiled: January 25, 2019Publication date: November 28, 2019Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
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Patent number: 10107975Abstract: A method for manufacturing an optoelectronic assembly includes attaching an optical die, a first lens, a second lens, and an optical fiber to a sub-mount. The sub-mount includes a plurality of passive alignment features which aid in the passive alignment of the optical die, the first lens, and the optical fiber for attachment. The second lens is actively aligned between the first lens and the optical fiber, based on a coupling efficiency with which an optical signal emitted by the optical die is coupled into the optical fiber through the first and second lenses. The active alignment of the second lens includes calibration of at least one of a position and a degree of tilt of the second lens.Type: GrantFiled: November 13, 2017Date of Patent: October 23, 2018Assignee: Denselight Semiconductors Pte. Ltd.Inventors: Yee Loy Lam, Long Cheng Koh, Kian Hin Victor Teo