Abstract: Disclosed are a three-dimensional measurement method for the key morphological features on an aircraft surface, a three-dimensional measurement system for the key morphological features on the aircraft surface, and a method for using the three-dimensional measurement system. In this method, the distribution characteristics of point clouds are fully utilized, and an angle is formed between a direction vector of the measurement point and a seam direction, which ensures that the point clouds can gradually approach the actual edge of the seam, and eliminates the impact of randomness. The point nearest to the seam in the point clouds on both sides of the seam is selected as the nearest point, which overcomes the limitation of the density of the point cloud, so that the distance between the selected nearest point and the actual edge of the seam is greatly reduced.

Abstract: A manufacturing method for a semiconductor device, comprising: providing a semiconductor substrate (100), and forming a shallow trench isolation structure (104) in the semiconductor substrate (100); forming a gate structure comprising a gate oxidation layer (105a) and a gate material layer (105b) that are stacked from the bottom up on the semiconductor substrate (100); executing first ion implantation so as to form first doping ions in the gate material layer (105b), and executing second ion implantation (109) so as to form second doping ions at the part of the gate material layer (105b) that is located over a top corner of the shallow trench isolation structure(104), the second doping ions and the first doping ions being opposite in conduction type.

Abstract: A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on

Abstract: A manufacturing method for a semiconductor device is provided.

Abstract: An Ethernet Ring Protection (ERP) method and the corresponding apparatus and communication equipment are disclosed. The method includes: when a link on an Ethernet ring network is faulty, judging whether the faulty link is a link where the normally blocked port is located; sending a control message which carries first indication information if the faulty link is the link where the normally blocked port is located; the ring node avoids clearing of a forwarding table after receiving the control message which carries the first indication information; sending the control message which carries second indication information if the faulty link is not the link where the normally blocked port is located; and the ring node clears the forwarding table after receiving the control message which carries the second indication information.