Abstract: A plurality of cassettes, each having a plurality of wafers respectively having a first defect information, is selected. Each of the cassettes is then assigned to a corresponding tool having at least one reaction chamber, and the wafers are substantially equally assigned to the reaction chambers. A first process is then performed on each of the wafers in the reaction chamber. Finally, a first defect inspection process is performed on each of the wafers.

Abstract: A wafer detection method. A plurality of PSL particles are sprayed on a wafer. An inspection operation is implemented on the wafer to obtain location information corresponding to a plurality of defects on the wafer, each location information corresponding to the defects comprises an error value. An inspection operation implemented on the PSL particles to obtain location information corresponding to the PSL particles. Offset location information corresponding to each defect is calculated according to the location information corresponding to each PSL particle. The error values corresponding to each defect are corrected according to the offset location information corresponding to each defect.

Abstract: A wafer detection method. A plurality of PSL particles are sprayed on a wafer. An inspection operation is implemented on the wafer to obtain location information corresponding to a plurality of defects on the wafer, each location information corresponding to the defects comprises an error value. An inspection operation implemented on the PSL particles to obtain location information corresponding to the PSL particles. Offset location information corresponding to each defect is calculated according to the location information corresponding to each PSL particle. The error values corresponding to each defect are corrected according to the offset location information corresponding to each defect.

Abstract: An inspection method for a semiconductor device is disclosed. The method includes providing a semiconductor device, performing heat treatment on the semiconductor device, and inspecting the semiconductor device utilizing electron beam to acquire an analysis image. The semiconductor device comprises a substrate, a plurality of gate electrodes protruding on the substrate, a blanket dielectric layer overlying the substrate and gate electrodes, and a plurality of polycrystalline silicon plugs, respectively disposed on the substrate between the gate electrodes, in the dielectric layer. A piping defect is detected by the analysis image showing an area with voltage contrast difference.

Abstract: A method of defect review. First, a wafer with a plurality of defects is provided. A defect inspection is performed to detect the defects. An automatic defect classification is then performed to divide the defects into different defect types according to a predetermined database. A defect review is performed to review different defect types of defects which are sampled in different weights according to yield killing ratios of each defect types.

Abstract: An inspection method for a semiconductor device is disclosed. The method includes providing a semiconductor device, performing heat treatment on the semiconductor device, and inspecting the semiconductor device utilizing electron beam to acquire an analysis image. The semiconductor device comprises a substrate, a plurality of gate electrodes protruding on the substrate, a blanket dielectric layer overlying the substrate and gate electrodes, and a plurality of polycrystalline silicon plugs, respectively disposed on the substrate between the gate electrodes, in the dielectric layer. A piping defect is detected by the analysis image showing an area with voltage contrast difference.

Abstract: First, a wafer with a plurality of defects generated in a first semiconductor process is provided. A defect inspection is performed to detect the defects on the wafer. Then, an automatic defect classification is performed according to a predetermined defect database having a defect classification recipe generated from a second semiconductor process. After that, a verifying process is further performed by comparing the result of the automatic defect classification with that of a manual defect classification to verify the accuracy of the automatic defect classification.

Abstract: A plurality of cassettes, each having a plurality of wafers respectively having a first defect information, is selected. Each of the cassettes is then assigned to a corresponding tool having at least one reaction chamber, and the wafers are substantially equally assigned to the reaction chambers. A first process is then performed on each of the wafers in the reaction chamber. Finally, a first defect inspection process is performed on each of the wafers.

Abstract: First, a wafer with a plurality of defects generated in a first semiconductor process is provided. A defect inspection is performed to detect the defects on the wafer. Then, an automatic defect classification is performed according to a predetermined defect database having a defect classification recipe generated from a second semiconductor process. After that, a verifying process is further performed by comparing the result of the automatic defect classification with that of a manual defect classification to verify the accuracy of the automatic defect classification.

Abstract: A method of defect review. First, a wafer with a plurality of defects is provided. A defect inspection is performed to detect the defects. An automatic defect classification is then performed to divide the defects into different defect types according to a predetermined database. A defect review is performed to review different defect types of defects which are sampled in different weights according to yield killing ratios of each defect types.

Abstract: A method of defect control by daily checking. First, a patterned wafer with a plurality of first defects is provided. After performing a semiconductor process, which generates a plurality of second defects on the wafer, a defect detecting process is performed to detect the first defects and the second defects. Then, the first defects and the second defects are divided according to a predetermined database. The second defects are classified into a plurality of defect types according to the predetermined database.

Abstract: A method of defect root cause analysis. First, a sample with a plurality defects thereon is provided. Then, a defect inspection is performed to detect the sizes and positions of the defects. After that, a chemical state analysis is performed, and a mapping analysis is made according to a result of the chemical state analysis. Thus, a root cause of defects can be obtained according to a result of the mapping analysis.

Abstract: A method of piping defect detection is disclosed. First, a sample is provided. The sample has a silicon substrate, a plurality of electric devices disposed on the silicon substrate surface, a dielectric layer covering the electric devices and the substrate, and a polysilicon layer positioned on the dielectric layer, which is electrically connected to the electric devices through contact holes in the dielectric layer. A chemical mechanical polish process is performed to remove the polysilicon layer on the dielectric layer and parts of the dielectric layer. A wet etching process is then performed to delayer the dielectric layer. After that, the sample is inspected under an ultraviolet light irradiation for detecting the piping defects in the dielectric layer of the sample.

Abstract: A method for automatically controlling defect-specification in a semiconductor manufacturing process is provided. The method provides a module to detect a position, number, size, and intensity signals of defects on a processed patterned wafer. The module further compares the patterned wafer with a normal wafer to preliminarily classify the patterned wafer and creates a defect map. Then, a defect management system is provided to execute a spatial pattern recognition procedure to determine whether or not the corresponding special pattern can be recognized. Finally, messages will be automatically sent by the defect management system to inform related e-mail accounts according to results of the recognition of the special pattern.

Abstract: A method for automatically controlling defect-specification in a semiconductor manufacturing process is provided. The method provides a module to detect a position, number, size, and intensity signals of defects on a processed patterned wafer. The module further compares the patterned wafer with a normal wafer to preliminarily classify the patterned wafer and creates a defect map. Then, a defect management system is provided to execute a spatial pattern recognition procedure to determine whether or not the corresponding special pattern can be recognized. Finally, messages will be automatically sent by the defect management system to inform related e-mail accounts according to results of the recognition of the special pattern.