Patents by Inventor Long Luo

Long Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12381702
    Abstract: Examples described herein include apparatuses and methods for full duplex device-to-device cooperative communication. Example systems described herein may include self-interference noise calculators. The output of a self-interference noise calculator may be used to compensate for the interference experienced due to signals transmitted by another antenna of the same wireless device or system. In implementing such a self-interference noise calculator, a selected wireless relaying device or wireless destination device may operate in a full-duplex mode, such that relayed messages may be transmitted as well as information from other sources or destinations during a common time period (e.g., symbol, slot, subframe, etc.).
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: August 5, 2025
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fa-Long Luo, Tamara Schmitz, Jeremy Chritz, Jaime Cummins
  • Publication number: 20250227394
    Abstract: Methods and apparatus for performing multi-step image processing using a reconfigurable fabric device (RFD) in place of multiple discrete ICs. In one embodiment, the methods and apparatus operate according to a flexible time-divided schedule, and the processing is configured to process image sensor data by at least: (i) receiving RAW image data, programming an RFD to operate as a first functional unit such as an image signal processor (ISP), using the programmed RFD to perform image signal processing on the RAW image data, storing the ISP-result in temporary memory; and (ii) programming the RFD to operate as a second functional unit (e.g., deep learning accelerator (DLA)), using the programmed RFD to read out ISP-result from the temporary memory, perform deep learning processing on the ISP-result, and storing the DLA-result back into the temporary memory. In one variant, an on-die controller and memory are used in support of the RFD operations, thereby enabling a single-die processing solution.
    Type: Application
    Filed: March 31, 2025
    Publication date: July 10, 2025
    Inventor: Fa-Long Luo
  • Patent number: 12353505
    Abstract: Methods and apparatus for performing diversity matrix operations within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for spatial diversity-related matrix transformations and performing matrix operations therein. Exemplary embodiments described herein perform MIMO-related matrix transformations (e.g., precoding, beamforming, or data recovery matrix operations) within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one variant, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a matrix-vector product.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: July 8, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Fa-Long Luo
  • Patent number: 12340117
    Abstract: Examples described herein include systems and methods which include a multiple input, multiple output transceiver including a plurality of receive antenna configured to receive a plurality of receive signals, and a wireless receiver coupled to the plurality of antenna and configured to receive and decode the plurality of receive signals. The transceiver includes a memory array and a memory controller. The memory controller includes a data address generator configured to, during the decode of the plurality of receive signals, generate at least one memory address according to an access mode of a memory command associated with a memory access operation. The at least one memory address corresponds to a specific sequence of memory access instructions to access a memory cell of the memory array.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: June 24, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Jaime Cummins
  • Publication number: 20250192982
    Abstract: A system and method to reduce fast Fourier transforms (FFT) required for bootstrapping in a Fully Homomorphic Encryption process. Ciphertext is separated into a vector of n samples. A fast Fourier transfer (FFT) is performed over a first vector of the samples. An FFT is performed for each of n polynomial terms multiplied by a bootstrap key. A point wise multiplication of each of the FFT outputs of the FFTs of the polynomial terms and the output of the FFT over the vector of the n samples is performed. The result of the FFT over the vector of the n samples is added to the results of the set of pointwise multiplications. An inverse FFT (IFFT) is performed on the FFT over the vector of n samples and the accumulated results of the point-wise multiplications to obtain a bootstrapping result of the ciphertext.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Fa-Long Luo, Paul Master
  • Publication number: 20250191969
    Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.
    Type: Application
    Filed: February 25, 2025
    Publication date: June 12, 2025
    Inventors: Glen E. Hush, Aaron P. Boehm, Fa-Long Luo
  • Publication number: 20250190570
    Abstract: A system and method to reduce fast Fourier transforms (FFT) required for bootstrapping in a Fully Homomorphic Encryption process. Ciphertext is separated into a vector of n samples. A fast Fourier transfer (FFT) is performed over a first vector of the samples and a FFT over a bootstrap key. A phase vector of n W(a) terms that are equivalents to the output of a FFT is calculated. A first set of pointwise multiplications of the FFT of the first vector of samples with each of the n W(a) terms in the phase vector is performed. A second set of pointwise multiplications of the results of the first set of pointwise multiplications with the FFT of the bootstrap key is performed. An inverse FFT(IFFT) on the accumulated result of the second set of point-wise multiplications is performed to obtain a bootstrapping result of the ciphertext.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Fa-Long Luo, Paul Master
  • Patent number: 12314723
    Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
    Type: Grant
    Filed: October 9, 2023
    Date of Patent: May 27, 2025
    Inventors: Glen E. Hush, Aaron P. Boehm, Fa-Long Luo
  • Publication number: 20250167811
    Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fa-Long Luo, Jaime Cummins
  • Publication number: 20250155231
    Abstract: A tape measure, a measuring device, and a measuring method are provided. The tape measure includes a first shell, a tape, an optical positioning assembly, and a first controller. The tape has one end mounted in the first shell and the other end extending out of the first shell and capable of moving in a first measuring direction relative to the first shell. An imaging sensor in the optical positioning assembly, when working, is capable of consecutively acquiring images of the tape in a moving process and then performing feature comparison on the images to determine a relative displacement of the tape moving in the first measuring direction in real time. Further, the controller of the tape measure is capable of determining, based on the relative displacement, a length by which the tape extends out of the first shell.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 15, 2025
    Applicant: Shenzhen Mileseey Technology Co., Ltd.
    Inventors: Long LUO, Zhi CHOU
  • Publication number: 20250147874
    Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Jaime Cummins, Tamara Schmitz, Jeremy Chritz
  • Patent number: 12267612
    Abstract: Methods and apparatus for performing multi-step image processing using a reconfigurable fabric device (RFD) in place of multiple discrete ICs. In one embodiment, the methods and apparatus operate according to a flexible time-divided schedule, and the processing is configured to process image sensor data by at least: (i) receiving RAW image data, programming an RFD to operate as a first functional unit such as an image signal processor (ISP), using the programmed RFD to perform image signal processing on the RAW image data, storing the ISP-result in temporary memory; and (ii) programming the RFD to operate as a second functional unit (e.g., deep learning accelerator (DLA)), using the programmed RFD to read out ISP-result from the temporary memory, perform deep learning processing on the ISP-result, and storing the DLA-result back into the temporary memory. In one variant, an on-die controller and memory are used in support of the RFD operations, thereby enabling a single-die processing solution.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Fa-Long Luo
  • Patent number: 12249377
    Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: March 11, 2025
    Inventors: Glen E. Hush, Aaron P. Boehm, Fa-Long Luo
  • Patent number: D1065227
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: March 4, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhiming Fan, Yi Han, Long Luo
  • Patent number: D1066080
    Type: Grant
    Filed: December 25, 2023
    Date of Patent: March 11, 2025
    Inventors: Jianjie Yang, Long Luo, Zhi Chou
  • Patent number: D1066081
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: March 11, 2025
    Inventors: Jianjie Yang, Long Luo, Zhi Chou
  • Patent number: D1074582
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: May 13, 2025
    Assignee: Shenzhen Green Giant Energy Technology Development Co., Ltd.
    Inventors: Xiaoming Yang, Long Luo
  • Patent number: D1083974
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: July 15, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yu Wu, Long Luo, Yi Han
  • Patent number: D1084088
    Type: Grant
    Filed: December 30, 2024
    Date of Patent: July 15, 2025
    Assignee: SHENZHEN MILESEEY TECHNOLOGY CO., LTD.
    Inventors: Jianjie Yang, Long Luo, Zhi Chou
  • Patent number: D1087146
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: August 5, 2025
    Assignee: HONOR DEVICE CO., LTD.
    Inventors: Guyu Xie, Long Luo, Ting Zhang