Abstract: The present invention provides a self-powered integrated sensing and communication (ISAC) interactive method of high-speed railway based on hierarchical deep reinforcement learning (HDRL), including: Constructing an integrated system framework for passive sensing and communication of high-speed train, where the passive sensor is mainly used for receiving train status information, and the access point (AP) is utilized for status information sensing of the train; During the remote communication between the AP and the base station (BS), Gaussian mixture model (GMM) clustering method is utilized for obtaining reference handover triggering points and completing the communication handover; Proposing an option-based HDRL algorithm to train the high-speed train agent so as to implement the dynamic autonomous switching process of information sensing and remote communication, thereby ensuring the minimum of task completion time and the timely charging for sensors.

Abstract: The present invention provides a self-powered integrated sensing and communication (ISAC) interactive method of high-speed railway based on hierarchical deep reinforcement learning (HDRL), including: Constructing an integrated system framework for passive sensing and communication of high-speed train, where the passive sensor is mainly used for receiving train status information, and the access point (AP) is utilized for status information sensing of the train; During the remote communication between the AP and the base station (BS), Gaussian mixture model (GMM) clustering method is utilized for obtaining reference handover triggering points and completing the communication handover; Proposing an option-based HDRL algorithm to train the high-speed train agent so as to implement the dynamic autonomous switching process of information sensing and remote communication, thereby ensuring the minimum of task completion time and the timely charging for sensors.

Abstract: A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the

Abstract: In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.

Abstract: A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the

Abstract: In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device.

Abstract: In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.