Abstract: A dual active bridge converter includes a first full-bridge circuit and a high-frequency inductor. The first full-bridge circuit includes a first bridge arm including a first switching element and a second switching element connected in series. Methods of controlling a dual active bridge converter include detecting a voltage of the high-frequency inductor in response to the first switching element being turned off, setting a dead time according to a detection result of the detecting the voltage of the high-frequency inductor, and turning on the second switching element based on the dead time.

Abstract: An IM device includes a magnetic core including a base plate, a cover plate, and first, second and third magnetic columns. A straight line defined by positions of the first and second magnetic columns is parallel to a length direction, and the third magnetic column is between the first and second magnetic columns, and extends in a width direction. A first coil is wound around the first magnetic column to generate a closed magnetic flux loop, a second coil wound around the second magnetic column to generate a closed magnetic flux loop. The magnetic core includes a fourth magnetic column between the base plate and the cover plate, and close to a first terminal of the third magnetic column in the width direction. In the length direction, the fourth magnetic column overlaps with at least a portion of the first magnetic column and at least a portion of the second magnetic column.

Abstract: An electronic switch includes a first NMOS transistor connected between a positive input terminal and an output terminal; a first diode, a second resistor, a first capacitor, and a third switching element sequentially connected in series between a drain of the first NMOS transistor and a negative input terminal; a first resistor connected between a positive input terminal and a node between the first capacitor and the third switching element; a third resistor connected between a gate of the first NMOS transistor and a node between the second resistor and the first capacitor; and a second capacitor, a second diode, and a fourth resistor connected in parallel between a source of the first NMOS transistor and a node between the third resistor and the gate of the first NMOS transistor.

Abstract: An electronic switch includes a first NMOS transistor connected between a positive input terminal and an output terminal; a first diode, a second resistor, a first capacitor, and a third switching element sequentially connected in series between a drain of the first NMOS transistor and a negative input terminal; a first resistor connected between a positive input terminal and a node between the first capacitor and the third switching element; a third resistor connected between a gate of the first NMOS transistor and a node between the second resistor and the first capacitor; and a second capacitor, a second diode, and a fourth resistor connected in parallel between a source of the first NMOS transistor and a node between the third resistor and the gate of the first NMOS transistor.

Abstract: An IM device includes a magnetic core including a base plate, a cover plate, and first, second and third magnetic columns. A straight line defined by positions of the first and second magnetic columns is parallel to a length direction, and the third magnetic column is between the first and second magnetic columns, and extends in a width direction. A first coil is wound around the first magnetic column to generate a closed magnetic flux loop, a second coil wound around the second magnetic column to generate a closed magnetic flux loop. The magnetic core includes a fourth magnetic column between the base plate and the cover plate, and close to a first terminal of the third magnetic column in the width direction. In the length direction, the fourth magnetic column overlaps with at least a portion of the first magnetic column and at least a portion of the second magnetic column.

Abstract: Exemplary embodiments of the present invention relate to a panel and a display device including the same, the panel including a substrate, a signal line arranged on the substrate, the signal line configured to transmit a driving signal, an insulating layer arranged on the signal line, and a pixel electrode and a contact assistant arranged on the insulating layer. The contact assistant is electrically connected to a portion of the signal line, the contact assistant includes indium zinc oxide doped with a metal oxide not including indium or zinc, and the metal oxide has a smaller Gibbs free energy than zinc oxide.

Abstract: A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.

Abstract: A thin film transistor array panel includes: a semiconductor layer disposed on an insulation substrate; a gate electrode overlapping the semiconductor layer; a source electrode and a drain electrode overlapping the semiconductor layer; a first barrier layer disposed between the source electrode and the semiconductor layer; and a second barrier layer disposed between the drain electrode and the semiconductor layer, wherein the first barrier layer and the second barrier layer include nickel-chromium (NiCr).

Abstract: A thin film transistor array panel is provided. The thin film transistor array panel includes a substrate, a seed layer positioned on the substrate, and a semiconductor layer positioned on the seed layer, wherein a lattice mismatch between the seed layer and the semiconductor layer is equal to or less than 1.4%.

Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.

Abstract: A thin film transistor array panel includes: a semiconductor layer disposed on an insulation substrate; a gate electrode overlapping the semiconductor layer; a source electrode and a drain electrode overlapping the semiconductor layer; a first barrier layer disposed between the source electrode and the semiconductor layer; and a second barrier layer disposed between the drain electrode and the semiconductor layer, wherein the first barrier layer and the second barrier layer include nickel-chromium (NiCr).

Abstract: A sputtering target includes a plurality of targets and edges of the targets overlap each other.

Abstract: Exemplary embodiments of the present invention relate to a panel and a display device including the same, the panel including a substrate, a signal line arranged on the substrate, the signal line configured to transmit a driving signal, an insulating layer arranged on the signal line, and a pixel electrode and a contact assistant arranged on the insulating layer. The contact assistant is electrically connected to a portion of the signal line, the contact assistant includes indium zinc oxide doped with a metal oxide not including indium or zinc, and the metal oxide has a smaller Gibbs free energy than zinc oxide.

Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.

Abstract: A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.

Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.