Patents by Inventor Long Pham
Long Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11959057Abstract: Embodiments of microfluidic systems and methods of manufacturing are described herein, which utilize an automated microfluidic plumbing technology with addressable ports capable of minimally disruptive additive and subtractive (including probing) cell and/or fluid manipulation at any desired location(s) within living cultures. The addressable microfluidic ports may be integrated throughout cell cultures in microfluidic systems for microfluidic tissue scaffolds, in two- or three-dimensional spatial arrangements. The addressable microfluidic ports may be used for controlling and/or monitoring cell behavior over time at different user-selected locations within cell cultures. Also provided are methods for fabricating such microfluidic devices and microfluidic tissue scaffolds.Type: GrantFiled: October 16, 2020Date of Patent: April 16, 2024Assignee: New Jersey Institute of TechnologyInventors: Roman Serheyevich Voronov, Quang Long Pham, Nguyen Nhat Anh Tong
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Patent number: 11955182Abstract: Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane pre-program operation incremented by the time increment parameter value. This approach solves the technical problem of Vt downshift for multi-plane pre-program operations, and thus, ensures that the success rate of secure erase operations does not diminish as the number of planes increases. This, in turn, allows for pre-program operations to be consistently performed on a multi-plane basis, which produces the technical effect of improved system performance.Type: GrantFiled: May 17, 2022Date of Patent: April 9, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Long Pham, Sai Gautham Thoppa
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Publication number: 20240095454Abstract: Techniques are provided for using context tags in named-entity recognition (NER) models. In one particular aspect, a method is provided that includes receiving an utterance, generating embeddings for words of the utterance, generating a regular expression and gazetteer feature vector for the utterance, generating a context tag distribution feature vector for the utterance, concatenating or interpolating the embeddings with the regular expression and gazetteer feature vector and the context tag distribution feature vector to generate a set of feature vectors, generating an encoded form of the utterance based on the set of feature vectors, generating log-probabilities based on the encoded form of the utterance, and identifying one or more constraints for the utterance.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Applicant: Oracle International CorporationInventors: Duy Vu, Tuyen Quang Pham, Cong Duy Vu Hoang, Srinivasa Phani Kumar Gadde, Thanh Long Duong, Mark Edward Johnson, Vishal Vishnoi
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Publication number: 20230386580Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Peng Wang, Jia Li, Behrang Bagheri, Keyur Payak, Bo Lei, Long Pham, Jun Wan
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Publication number: 20230377656Abstract: Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane pre-program operation incremented by the time increment parameter value. This approach solves the technical problem of Vt downshift for multi-plane pre-program operations, and thus, ensures that the success rate of secure erase operations does not diminish as the number of planes increases. This, in turn, allows for pre-program operations to be consistently performed on a multi-plane basis, which produces the technical effect of improved system performance.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Inventors: Long PHAM, Sai Gautham THOPPA
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Publication number: 20210115368Abstract: Embodiments of microfluidic systems and methods of manufacturing are described herein, which utilize an automated microfluidic plumbing technology with addressable ports capable of minimally disruptive additive and subtractive (including probing) cell and/or fluid manipulation at any desired location(s) within living cultures. The addressable microfluidic ports may be integrated throughout cell cultures in microfluidic systems for microfluidic tissue scaffolds, in two- or three-dimensional spatial arrangements. The addressable microfluidic ports may be used for controlling and/or monitoring cell behavior over time at different user-selected locations within cell cultures. Also provided are methods for fabricating such microfluidic devices and microfluidic tissue scaffolds.Type: ApplicationFiled: October 16, 2020Publication date: April 22, 2021Inventors: Roman Serheyevich Voronov, Quang Long Pham, Nguyen Nhat Anh Tong
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Patent number: 10854306Abstract: A state of one or more fuses can be determined using a common-gate FET device to read reference information and test information from a fuse bank. In an example, the FET device can be selectively diode-connected using a first switch that responds to a control signal, and a signal-storing capacitor can be connected to the gate terminal of the FET device. The capacitor can store information about a reference signal when the first switch is closed and a first input signal is applied at a source node of the FET device. When the first switch is open, a second input signal can be applied at the source node of the FET device, and an output signal at the drain node of the FET device can indicate a magnitude relationship between the first input signal and the reference signal. In an example, the second input signal can indicate a state of a fuse.Type: GrantFiled: September 19, 2019Date of Patent: December 1, 2020Assignee: Analog Devices, Inc.Inventors: Howard R. Samuels, Long Pham
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Patent number: 10819365Abstract: Improved switching techniques for controlling three-level current steering DAC cells are disclosed. The techniques include decoupling two current sources, implemented as field-effect transistors (FETs), of a DAC cell both from their respective bias sources and from a load for converting a zero digital input, where the decoupling is performed in a certain order. The techniques also include coupling the current sources to their respective bias sources and to the load for converting a non-zero digital input, where the coupling is also performed in a certain order. The certain order of decoupling and coupling the bias sources and the load to the current sources of a DAC cell are based on the phenomenon of current memory in FETs. Utilizing current memory when operating a DAC cell may allow reducing power consumption while preserving the high performance properties of a three-level current steering DAC.Type: GrantFiled: February 6, 2020Date of Patent: October 27, 2020Assignee: ANALOG DEVICES, INC.Inventors: Khiem Quang Nguyen, Long Pham
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Patent number: 10529435Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.Type: GrantFiled: January 5, 2018Date of Patent: January 7, 2020Assignee: SanDisk Technologies LLCInventors: Sarath Puthenthermadam, Deepanshu Dutta, Long Pham
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Publication number: 20190214100Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.Type: ApplicationFiled: January 5, 2018Publication date: July 11, 2019Applicant: SanDisk Technologies LLCInventors: Sarath Puthenthermadam, Deepanshu Dutta, Long Pham
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Patent number: 10089021Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. An integrated circuit chip comprising non-volatile memory, the integrated circuit chip configured to, determine a number of portions into which a storage operation is to be split; pause execution of the storage operation from within the integrated circuit chip according to the determined number of portions; execute one or more other storage operations on the integrated circuit chip while the storage operation is paused, each of the one or more other storage operations having a shorter duration than the storage operation; and continue the paused storage operation in response to a trigger.Type: GrantFiled: March 22, 2018Date of Patent: October 2, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jea Hyun, James Peterson, Long Pham, John Strasser, Hairong Sun, Kapil Verma
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Publication number: 20180210661Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. An integrated circuit chip comprising non-volatile memory, the integrated circuit chip configured to, determine a number of portions into which a storage operation is to be split; pause execution of the storage operation from within the integrated circuit chip according to the determined number of portions; execute one or more other storage operations on the integrated circuit chip while the storage operation is paused, each of the one or more other storage operations having a shorter duration than the storage operation; and continue the paused storage operation in response to a trigger.Type: ApplicationFiled: March 22, 2018Publication date: July 26, 2018Applicant: SanDisk Technologies LLCInventors: Jea Hyun, James Peterson, Long Pham, John Strasser, Hairong Sun, Kapil Verma
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Patent number: 9933950Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. A frequency module is configured to determine a frequency for pausing a storage operation. An interrupt module is configured to pause execution of a storage operation according to a determined frequency. A resume module is configured to continue a paused storage operation in response to a trigger.Type: GrantFiled: March 12, 2015Date of Patent: April 3, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jea Hyun, James Peterson, Long Pham, John Strasser, Hairong Sun, Kapil Verma
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Publication number: 20160210050Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. A frequency module is configured to determine a frequency for pausing a storage operation. An interrupt module is configured to pause execution of a storage operation according to a determined frequency. A resume module is configured to continue a paused storage operation in response to a trigger.Type: ApplicationFiled: March 12, 2015Publication date: July 21, 2016Inventors: Jea Hyun, James Peterson, Long Pham, John Strasser, Hairong Sun, Kapil Verma
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Publication number: 20120042002Abstract: A system and method for context driven centralized help is provided. A daemon application initiated on a workstation or mobile device is configured to intercept a help request received in connection with an active application when a pre-defined triggering event is invoked. The daemon application captures context corresponding to the current page or function in use with the active application and generates a corresponding information dataset pertaining to the captured context. The information dataset is transmitted to a remote site, configured to query a content database, to determine if help-related content has been previously associated with the captured context, wherein a positive determination of the existence of such an association results in the help-related content being retrieved and displayed on the workstation or mobile device.Type: ApplicationFiled: June 3, 2009Publication date: February 16, 2012Inventors: Tony Paul Smith, Julian Hartley Cork, Tuan Long Pham, Milind Kulkarni, Sergejs Olhoviks, Vince Sethi, Anthony Brian Knife, Tarik Cherkaoui, Richard Alexander Hill
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Patent number: 7715255Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.Type: GrantFiled: June 14, 2007Date of Patent: May 11, 2010Assignee: SanDisk CorporationInventors: Loc Tu, Jian Chen, Alex Mak, Tien-Chien Kuo, Long Pham
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Patent number: 7492634Abstract: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.Type: GrantFiled: September 26, 2007Date of Patent: February 17, 2009Assignee: SanDisk CorporationInventors: Yan Li, Long Pham
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Patent number: 7477545Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.Type: GrantFiled: June 14, 2007Date of Patent: January 13, 2009Assignee: SanDisk CorporationInventors: Loc Tu, Jian Chen, Alex Mak, Tien-Chien Kuo, Long Pham
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Publication number: 20080311684Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.Type: ApplicationFiled: June 14, 2007Publication date: December 18, 2008Inventors: Loc Tu, Jian Chen, Alex Mak, Tien-chien Kuo, Long Pham
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Publication number: 20080310242Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.Type: ApplicationFiled: June 14, 2007Publication date: December 18, 2008Inventors: Loc Tu, Jian Chen, Alex Mak, Tien-chien Kuo, Long Pham