Patents by Inventor Long Shih Lin
Long Shih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11233121Abstract: A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5×1012 ions/cm3 to about 5×1013 ions/cm3, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.Type: GrantFiled: June 15, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Hsiung Yang, Long-Shih Lin, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu
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Publication number: 20200312957Abstract: A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5×1012 ions/cm3 to about 5×1013 ions/cm3, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Fu-Hsiung YANG, Long-Shih LIN, Kun-Ming HUANG, Chih-Heng SHEN, Po-Tao CHU
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Patent number: 10686036Abstract: A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.Type: GrantFiled: May 4, 2017Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Hsiung Yang, Long-Shih Lin, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu
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Patent number: 10002761Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.Type: GrantFiled: July 6, 2015Date of Patent: June 19, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
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Patent number: 9853121Abstract: A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.Type: GrantFiled: July 2, 2015Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Long-Shih Lin, Kun-Ming Huang, Ming-Yi Lin
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Publication number: 20170236904Abstract: A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.Type: ApplicationFiled: May 4, 2017Publication date: August 17, 2017Inventors: Fu-Hsiung YANG, Long-Shih LIN, Kun-Ming HUANG, Chih-Heng SHEN, Po-Tao CHU
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Patent number: 9698024Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.Type: GrantFiled: July 14, 2014Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu
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Patent number: 9647065Abstract: A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.Type: GrantFiled: October 17, 2013Date of Patent: May 9, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Hsiung Yang, Long-Shih Lin, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu
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Publication number: 20150311070Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.Type: ApplicationFiled: July 6, 2015Publication date: October 29, 2015Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
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Publication number: 20150303276Abstract: A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.Type: ApplicationFiled: July 2, 2015Publication date: October 22, 2015Inventors: Long-Shih LIN, Kun-Ming HUANG, Ming-Yi LIN
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Patent number: 9111898Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.Type: GrantFiled: February 19, 2013Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu
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Patent number: 9076837Abstract: A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.Type: GrantFiled: July 6, 2012Date of Patent: July 7, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Long-Shih Lin, Kun-Ming Huang, Ming-Yi Lin
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Publication number: 20150108542Abstract: A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Hsiung YANG, Long-Shih LIN, Kun-Ming HUANG, Chih-Heng SHEN, Po-Tao CHU
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Publication number: 20140322871Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.Type: ApplicationFiled: July 14, 2014Publication date: October 30, 2014Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu
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Publication number: 20140231964Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.Type: ApplicationFiled: February 19, 2013Publication date: August 21, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu
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Patent number: 8779555Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.Type: GrantFiled: December 6, 2012Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
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Publication number: 20140159103Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
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Publication number: 20140008723Abstract: A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Long-Shih LIN, Kun-Ming HUANG, Ming-Yi LIN
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Patent number: 8125008Abstract: A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.Type: GrantFiled: November 17, 2006Date of Patent: February 28, 2012Assignee: System General CorporationInventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin
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Patent number: 7732890Abstract: The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.Type: GrantFiled: June 28, 2006Date of Patent: June 8, 2010Assignee: System General Corp.Inventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin