Abstract: A method for preparing temsirolimus, the method including: using a substituted aromatic aldehyde to protect 2,2-dimethylol propionic acid to produce intermediate II; carrying out reaction between the intermediate II and 2,4,6-trichlorobenzoyl chloride; carrying out condensation reaction between a resulting product and rapamycin to produce intermediate III; and finally using sulfuric acid to remove a protecting group from the intermediate III to yield temsirolimus.

Abstract: A zoom lens includes a first lens unit, a second lens unit, a third lens unit and a fourth lens unit. The third lens unit includes a movable barrel, a first slidable member able to move in a first direction perpendicular to the optical axis, and a second slidable member able to move along a second direction perpendicular to the optical axis and also perpendicular to the first direction. The movable barrel includes a first Hall member and a first coil, the first slidable member comprises a second Hall member and a second coil. A first magnet is aligned with the first coil, and a second magnet is aligned with the second coil, both coils can be independently energized to compensate any shaking movements experienced by the Hall members.

Abstract: A zoom lens includes a first lens unit, a second lens unit, a third lens unit and a fourth lens unit. The third lens unit includes a movable barrel, a first slidable member able to move in a first direction perpendicular to the optical axis, and a second slidable member able to move along a second direction perpendicular to the optical axis and also perpendicular to the first direction. The movable barrel includes a first Hall member and a first coil, the first slidable member comprises a second Hall member and a second coil. A first magnet is aligned with the first coil, and a second magnet is aligned with the second coil, both coils can be independently energized to compensate any shaking movements experienced by the Hall members.

Abstract: A punch device includes a mounting platform, a punch mechanism, a feeding mechanism, and a positioning and ejecting mechanism. The punch mechanism is mounted over the mounting platform for punching a pre-punched workpiece positioned on the mounting platform. The feeding mechanism is mounted on the mounting platform for conveying the pre-punched workpiece. The positioning and ejecting mechanism is mounted on the mounting platform and positioned under the punch mechanism, for positioning the pre-punched workpiece during a punching process, and ejecting the punched workpiece after the punching process is performed, thereby facilitating an operator to take away the punched workpiece.

Abstract: A method and apparatus to eliminate contaminants in a lithography process for fabrication of integrated circuit devices. The method includes depositing a photoresist material on surface of a semiconductor substrate. A purge gas flow is provided proximate to an optical element to prevent a vapor from the exposed photoresist material from coming into contact with the optical element. In one embodiment, the purge gas flows into a perforated and open ended enclosure in which the optical element is provided in the form of a lens. One open end of the enclosure is coupled to the lens and the other open end is positioned above the surface of the semiconductor substrate. Perforation of the enclosure facilitates movement of purge gas thereto, eliminating contact with the vapor from the developed resist and unwanted deposition of a solid contamination on the lens.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: A method and apparatus to eliminate contaminants in a lithography process for fabrication of integrated circuit devices. The method includes depositing a photoresist material on surface of a semiconductor substrate. A purge gas flow is provided proximate to an optical element to prevent a vapor from the exposed photoresist material from coming into contact with the optical element. In one embodiment, the purge gas flows into a perforated and open ended enclosure in which the optical element is provided in the form of a lens. One open end of the enclosure is coupled to the lens and the other open end is positioned above the surface of the semiconductor substrate. Perforation of the enclosure facilitates movement of purge gas thereto, eliminating contact with the vapor from the developed resist and unwanted deposition of a solid contamination on the lens.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A content addressable memory (CAM) is used to store the address of the semaphore and is checked by devices attempting to access the memory to determine whether the memory is available before an address is placed on the memory bus.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A content addressable memory (CAM) is used to store the address of the semaphore and is checked by devices attempting to access the memory to determine whether the memory is available before an address is placed on the memory bus.

Abstract: An integrated circuit preamplifier amplifies an input signal comprising first and second differential input signals to provide an amplified output signal comprising first and second differential output signals. A biasing circuit of the preamplifier provides a bias current. An open-loop differential amplifier of the preamplifier is coupled to the biasing circuit. The differential amplifier includes a differential amplifier pair having first and second differential amplifying transistors, which are coupled at respective gate terminals to the first and second differential input signals. Each of the amplifying transistors are coupled in open-loop configuration at a drain terminal to a respective load resistor coupled to ground, and the source terminals of the amplifying transistors are coupled together to receive the bias current. The first and second differential output signals are formed across the respective first and second load resistors.

Abstract: A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption. The system also includes a tracker to keep track of the number of times each of the factors occurs and a priority changer to change the priority of the devices as a function of the intrinsic priority and the number.

Abstract: A system for transferring data in a microprocessor architecture including a memory array unit (MAU) and multiple devices seeking access to the MAU. The system has a row match circuit for detecting and indicating a row match between successive row addresses. The row match circuit include a latch for storing a previous row address request, and a comparator for comparing a previously latched row address request with a present row address request associated with a specific device of the multiple devices seeking access to the MAU. The comparator asserts a row match signal when the previously latched row address request matches the present row address request. The system further includes an arbiter for controlling priorities associated with the multiple devices seeking access to the MAU.

Abstract: A method and apparatus for adjusting the resistance across a slave transistor to follow a master resistor network are disclosed. A tuning circuit is disclosed which is used to control the effective resistance of a slave transistor for use in high speed integrated automatic gain control, equalizer, filter or equivalent types of circuits where low parasitic capacitance is desired. The invention provides a way to replace a resistor network and its associated high parasitic capacitance with an equivalent resistance having low parasitic capacitance. The invention replaces the resistor network, having large parasitic capacitance, with a slave transistor exhibiting an equivalent resistance, having low parasitic capacitance. An automatic tuning circuit containing a resistor network is located remotely to a circuit containing a slave transistor. The tuning circuit is then used to adjust the effective resistance of the slave transistor.

Abstract: An on-site monitor is disclosed for providing automatic measurements of chemical concentrations in a liquid or gaseous environment. The opto-electronic monitor has an extended probe, which can be inserted into the liquid or to be in contact with the ambiance, comprising a indicator chamber for continuously supplying fresh indicator material, a light source, and a detector. The light source and the detector are either embodied outside of liquid or into the extended plastic probe inside the liquid. A delivery unit, which is activated by a timer, delivers a small amount of indicator material into the liquid or a sampling cavity. The indicator material reacts with the ions in the liquid automatically. The light source has a wavelength which matches with the indicator's absorption wavelength and the detector measures the transmission (or reflection) through the indicator material or solution.

Abstract: The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end products, and the 64 bit bus would be used for high end products. A memory control unit (MCU) supports both the 32 bit and 64 bit modes. Selecting a 32 bit or 64 bit memory subsystem gives a user more room to adjust system cost and performance.

Abstract: An integrated circuit differential amplifier with a digitally controllable gain. In a preferred embodiment, the differential amplifier employs first and second transconductance (gm) amplifiers and a digital to analog converter (DAC). The first gm amplifier converts a differential input voltage into a differential output current and the second gm amplifier converts the differential output current into a differential output voltage. A digital input code is applied to the DAC to generate an analog output voltage that is applied to one of the gm amplifiers to control its transconductance to thereby control the gain of the differential amplifier. The second gm amplifier employs a pair of low impedance feedback paths between input/output terminals of opposite polarity. The gain of the differential amplifier is thus a function of the ratio of the transconductance of the first gm amplifier to that of the second gm amplifier.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes.