Abstract: A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.

Abstract: In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

Abstract: In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

Abstract: In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

Abstract: In one embodiment, a receiver has an equalizer, a tap-averaging block, a delay buffer, and a filter. The equalizer receives an input signal from upstream processing and generates sets of filter coefficients. Each set of filter coefficients is adaptively generated by 1) filtering the received signal to generate an equalized signal, 2) calculating an error of the equalized signal, and 3) generating a new set of coefficients based on the error of the equalized signal. The sets of filter coefficients are output to the tap-averaging block, which averages groups of the sets of filter coefficients to generate sets of averaged filter coefficients, where each averaged set is output to the filter. The filter receives a time-delayed version of the input signal from the delay buffer and applies the current set of averaged filter coefficients to the time-delayed signal. The filtered signal is then output to downstream processing.

Abstract: In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power.

Abstract: In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

Abstract: In one embodiment, a receiver has an equalizer, a tap-averaging block, a delay buffer, and a filter. The equalizer receives an input signal from upstream processing and generates sets of filter coefficients. Each set of filter coefficients is adaptively generated by 1) filtering the received signal to generate an equalized signal, 2) calculating an error of the equalized signal, and 3) generating a new set of coefficients based on the error of the equalized signal. The sets of filter coefficients are output to the tap-averaging block, which averages groups of the sets of filter coefficients to generate sets of averaged filter coefficients, where each averaged set is output to the filter. The filter receives a time-delayed version of the input signal from the delay buffer and applies the current set of averaged filter coefficients to the time-delayed signal. The filtered signal is then output to downstream processing.

Abstract: A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.