Patents by Inventor LONGFEI BAI

LONGFEI BAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12332807
    Abstract: The present disclosure provides a data processing method and apparatus, an electronic device, and a storage medium. The data processing provided by the present disclosure includes: receiving a first request message from a first device, where the first request message includes a first address aligned with a first data length and a first size in a unit of the first data length; converting the first address into a second address aligned with a second data length, where the second data length is greater than the first data length; converting the first size into a second size in a unit of the second data length; and sending a second request message to a second device, where the second request message includes the second address and the second size.
    Type: Grant
    Filed: June 28, 2024
    Date of Patent: June 17, 2025
    Assignees: Beijing Youzhuju Network Technology Co., Ltd., Lemon Inc
    Inventors: Zhilin Xu, Qi Chen, Longfei Bai, Yimin Chen, Jian Wang
  • Publication number: 20250028649
    Abstract: The present disclosure provides a data processing method and apparatus, an electronic device, and a storage medium. The data processing provided by the present disclosure includes: receiving a first request message from a first device, where the first request message includes a first address aligned with a first data length and a first size in a unit of the first data length; converting the first address into a second address aligned with a second data length, where the second data length is greater than the first data length; converting the first size into a second size in a unit of the second data length; and sending a second request message to a second device, where the second request message includes the second address and the second size.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 23, 2025
    Inventors: Zhilin XU, Qi CHEN, Longfei BAI, Yimin CHEN, Jian WANG
  • Publication number: 20240378022
    Abstract: A data conversion method and apparatus, an electronic device and a storage medium for converting dimensions of a first data combination. The data conversion method includes: reading n elements in the first data combination according to a first-dimension direction to obtain a first processing group, a first element to an n-th element in the first processing group are arranged according to the first-dimension direction, and n is a positive integer; performing a transpose on the first dimension and the third dimension of the first processing group to obtain a second processing group, a first element to an n-th element in the second processing group are arranged in a third-dimension direction; and writing the first element to the n-th element in the second processing group to a first storage.
    Type: Application
    Filed: May 3, 2024
    Publication date: November 14, 2024
    Inventors: Zhilin XU, Longfei BAI, Qi CHEN, Yimin Chen, Shan Lu, Jian Wang
  • Publication number: 20240354368
    Abstract: A method and a system for performing a matrix multiplication operator using a unit supporting convolution operator operation, an electronic device, and a non-transitory storage medium are provided. The method includes: transforming a first matrix of the matrix multiplication operator to an input data matrix of a convolution operator; transforming a second matrix of the matrix multiplication operator to a weight matrix of the convolution operator, matrix multiplication being performed on the first matrix and the second matrix; and performing a convolution operation on the input data matrix and the weight matrix, which are obtained through transforming, of the convolution operator using the unit supporting convolution operator operation to obtain an operation result of the matrix multiplication operator.
    Type: Application
    Filed: April 23, 2024
    Publication date: October 24, 2024
    Inventors: Longfei BAI, Qi CHEN, Zhitao YANG, Zhilin XU, Yimin CHEN, Shan LU, Jian WANG
  • Patent number: 10073698
    Abstract: A processor has an execution pipeline that executes microinstructions and an instruction translator that translates architectural instructions into the microinstructions. The instruction translator has a memory that holds microcode instructions and provides a fetch quantum of a plurality of microcode instructions per clock cycle, a queue that holds microcode instructions provided by the memory, and a branch decoder that decodes the fetch quantum to detect local branch instructions, causes microcode instructions of the fetch quantum up to but not including a first-in-program-order local branch instruction to be written to the queue, and prevents the first-in-program-order local branch instruction and following microcode instructions of the fetch quantum from being written to the queue. Local branch instructions are resolved by the instruction translator rather than the execution pipeline.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: September 11, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Longfei Bai, Zhenhua Huang, Mengmeng Yan
  • Publication number: 20180095753
    Abstract: A processor has an execution pipeline that executes microinstructions and an instruction translator that translates architectural instructions into the microinstructions. The instruction translator has a memory that holds microcode instructions and provides a fetch quantum of a plurality of microcode instructions per clock cycle, a queue that holds microcode instructions provided by the memory, and a branch decoder that decodes the fetch quantum to detect local branch instructions, causes microcode instructions of the fetch quantum up to but not including a first-in-program-order local branch instruction to be written to the queue, and prevents the first-in-program-order local branch instruction and following microcode instructions of the fetch quantum from being written to the queue. Local branch instructions are resolved by the instruction translator rather than the execution pipeline.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 5, 2018
    Inventors: LONGFEI BAI, ZHENHUA HUANG, MENGMENG YAN