Abstract: A method for manufacturing a trench gate device includes: forming a trench in a substrate with a super junction structure; forming a gate dielectric layer in the trench; forming a polysilicon gate by filling a portion of the trench with polysilicon; forming an intermediate dielectric layer in the trench; forming an auxiliary polysilicon layer by filling a gap in the trench with polysilicon; forming a source region of the trench gate device in the substrate; depositing an interlayer dielectric layer, and forming contacts in the interlayer dielectric layer, wherein the polysilicon gate, the auxiliary polysilicon layer, and the source region are led out from the contacts; and connecting the led-out auxiliary polysilicon layer to the led-out source region.

Abstract: The present disclosure discloses a trench gate semiconductor device, wherein a trench gate includes a trench formed in a semiconductor substrate, and a gate oxide layer formed on a bottom surface and a side surface of the trench; the gate oxide layer is formed by stacking a first oxide layer and a second oxide layer; the first oxide layer is a furnace tube thermal oxide layer; the second oxide layer is a PECVD oxide layer; the gate oxide layer has a thermally densified structure processed by means of RTA. The present disclosure also discloses a method for manufacturing a trench gate semiconductor device. The present disclosure can increase BVGSS of the device, without affecting the threshold voltage of the device, with simple processes and low costs.

Abstract: A method for manufacturing a trench gate device includes: forming a trench in a substrate with a super junction structure; forming a gate dielectric layer in the trench; forming a polysilicon gate by filling a portion of the trench with polysilicon; forming an intermediate dielectric layer in the trench; forming an auxiliary polysilicon layer by filling a gap in the trench with polysilicon; forming a source region of the trench gate device in the substrate; depositing an interlayer dielectric layer, and forming contacts in the interlayer dielectric layer, wherein the polysilicon gate, the auxiliary polysilicon layer, and the source region are led out from the contacts; and connecting the led-out auxiliary polysilicon layer to the led-out source region.

Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and an emitter region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.

Abstract: The present disclosure discloses a trench gate semiconductor device, wherein a trench gate includes a trench formed in a semiconductor substrate, and a gate oxide layer formed on a bottom surface and a side surface of the trench; the gate oxide layer is formed by stacking a first oxide layer and a second oxide layer; the first oxide layer is a furnace tube thermal oxide layer; the second oxide layer is a PECVD oxide layer; the gate oxide layer has a thermally densified structure processed by means of RTA. The present disclosure also discloses a method for manufacturing a trench gate semiconductor device. The present disclosure can increase BVGSS of the device, without affecting the threshold voltage of the device, with simple processes and low costs.

Abstract: A super-junction structure is formed by alternately arrayed pluralities of N-pillars and of P-pillars. The P-pillars are formed by P-type materials filled in super-junction trenches. The super-junction trenches are formed in an N-type epitaxial layer, each formed by a bottom trench and a top trench stacked together. A side angle of the bottom trenches is greater than 90°, and the width of the bottom surface of each bottom trench is greater than that of the top surface of the trench. The side angle of the top trenches is smaller than 90°, and the width of the bottom surface of each top trench is smaller than the top surface of the trench. The super-junction trenches are of a waisted structure. The bottom trenches increase the bottom width of the super-junction trenches and improve the depletion of the bottoms of the N-pillars, increasing the breakdown voltage of the super-junction structure.

Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and a source region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.

Abstract: A trench gate manufacturing method includes the following steps: Step 1, forming a trench in the surface of a semiconductor substrate; Step 2, forming a first oxide layer; Step 3, selecting a coating according to the depth-to-width ratio of the trench and forming the coating completely filling the trench; Step 4, etching back the coating through a dry etching process; Step 5, conducting wet etching on the first oxide layer with the coating reserved at the bottom of the trench as a mask so as to form a gate bottom oxide; Step 6, removing the coating; and Step 7, growing a gate oxide. By adoption of the trench gate manufacturing method, a BTO can be realized at a low cost, and can be well-formed in trenches with smaller depth-to-width ratios and thus is suitable for forming BTOs in trenches with various depth-to-width ratios, thereby having a wider application range.

Abstract: A super-junction structure is formed by alternately arrayed pluralities of N-pillars and of P-pillars. The P-pillars are formed by P-type materials filled in super-junction trenches. The super-junction trenches are formed in an N-type epitaxial layer, each formed by a bottom trench and a top trench stacked together. A side angle of the bottom trenches is greater than 90°, and the width of the bottom surface of each bottom trench is greater than that of the top surface of the trench. The side angle of the top trenches is smaller than 90°, and the width of the bottom surface of each top trench is smaller than the top surface of the trench. The super-junction trenches are of a waisted structure. The bottom trenches increase the bottom width of the super-junction trenches and improve the depletion of the bottoms of the N-pillars, increasing the breakdown voltage of the super-junction structure.

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

Abstract: A trench gate manufacturing method includes the following steps: Step 1, forming a trench in the surface of a semiconductor substrate; Step 2, forming a first oxide layer; Step 3, selecting a coating according to the depth-to-width ratio of the trench and forming the coating completely filling the trench; Step 4, etching back the coating through a dry etching process; Step 5, conducting wet etching on the first oxide layer with the coating reserved at the bottom of the trench as a mask so as to form a gate bottom oxide; Step 6, removing the coating; and Step 7, growing a gate oxide. By adoption of the trench gate manufacturing method, a BTO can be realized at a low cost, and can be well-formed in trenches with smaller depth-to-width ratios and thus is suitable for forming BTOs in trenches with various depth-to-width ratios, thereby having a wider application range.

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching

Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching