Patents by Inventor Longjuan Tang

Longjuan Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894231
    Abstract: Semiconductor structures and fabrication methods thereof are provided. The method may include providing a to-be-etched layer; forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers and a width of the first opening is smaller than a width of the second opening; forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers; forming a second sacrificial layer on a portion of the first sacrificial material layer in the first opening to form a sacrificial structure in the first opening; removing the plurality of core layers after forming the sacrificial structure; forming sidewall spacers on sidewall surfaces of the sacrificial structure after removing the plurality of core layers; and removing the sacrificial structure after forming the sidewall spacers.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 6, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Longjuan Tang, Chenxi Yang
  • Patent number: 11205596
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. The method further includes forming a sidewall dielectric layer on sidewalls of the first contact hole, and using an etch process with the sidewall dielectric layer as an etch mask, etching the interlayer dielectric layer at bottom of the first contact hole to form a second contact hole extending to the active region.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: December 21, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Longjuan Tang
  • Publication number: 20210320007
    Abstract: Semiconductor structures and fabrication methods thereof are provided. The method may include providing a to-be-etched layer; forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers and a width of the first opening is smaller than a width of the second opening; forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers; forming a second sacrificial layer on a portion of the first sacrificial material layer in the first opening to form a sacrificial structure in the first opening; removing the plurality of core layers after forming the sacrificial structure; forming sidewall spacers on sidewall surfaces of the sacrificial structure after removing the plurality of core layers; and removing the sacrificial structure after forming the sidewall spacers.
    Type: Application
    Filed: March 22, 2021
    Publication date: October 14, 2021
    Inventors: Haiyang ZHANG, Longjuan TANG, Chenxi YANG
  • Publication number: 20180144990
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. The method further includes forming a sidewall dielectric layer on sidewalls of the first contact hole, and using an etch process with the sidewall dielectric layer as an etch mask, etching the interlayer dielectric layer at bottom of the first contact hole to form a second contact hole extending to the active region.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 24, 2018
    Inventors: QIUHUA HAN, Longjuan Tang