Patents by Inventor Longkang YANG

Longkang YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12154943
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well region of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 26, 2024
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Conghui Liu, Huan Wang, Longkang Yang
  • Patent number: 12154944
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device). When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: November 26, 2024
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Conghui Liu, Huan Wang, Longkang Yang
  • Patent number: 12136647
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. A floating island of a second conductivity type of a cell region, a floating island of the second conductivity type of a termination region, a pillar of the second conductivity type of the cell region and a pillar of the second conductivity type of the termination region may be formed through adding a super junction mask (or reticle) after forming the epitaxial layer of a first conductivity type, through a well mask (or reticle) before or after forming a well of the second conductivity type, and through a contact mask (or reticle) before or after forming a contact structure. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 5, 2024
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Conghui Liu, Huan Wang, Longkang Yang, Richard Ru-Gin Chang
  • Publication number: 20230326962
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device). When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 12, 2023
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Conghui LIU, Huan WANG, Longkang YANG
  • Patent number: 11715758
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 1, 2023
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Conghui Liu, Huan Wang, Longkang Yang
  • Patent number: 11677019
    Abstract: The present application provides an insulated gate bipolar transistor (IGBT) device with narrow mesa and a manufacture thereof. The device comprises: a semiconductor substrate; gate trench structures and emitter trench structures formed on front surface of the semiconductor substrate and alternately arranged along with horizontal direction; wherein the gate trench structures and the emitter trench structures are respectively set in pair along with the arrangement direction, and the pairs of the gate trench structures and the pairs of the emitter trench structures are set in alternate arrangement along with the arrangement direction; well regions formed between the emitter trench structures of one pair; emitter injection regions formed between the gate trench structures of one pair and between the emitter trench structures of one pair, respectively; and wherein, in the region between the emitter trench structures of the one pair, the emitter injection region is above the well region.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: June 13, 2023
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Ching-Ju Lin, Ying-Tsung Wu, Conghui Liu, Longkang Yang, Huan Wang, Richard Ru-Gin Chang
  • Patent number: 11456367
    Abstract: The present invention provides a trench gate structure and a method of forming the same. The method comprises steps of forming a first trench on the surface of a substrate, a surface of a bottom of the first trench comprising a crystal face belonging to the first family of crystal faces, and a surface of a sidewall of the first trench comprising another crystal face belonging to a second family of crystal faces. With a face-selective wet etching, a specific crystal face is presented on the surface of the bottom of the trench and a thicker gate oxide layer is formed thereon after performing thermal oxidation to avoid from failure due to thinner gate oxide layer on the surface of the bottom, increase breakdown voltage, and improve reliability of the device.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 27, 2022
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Longkang Yang, Huaihua Xu, Huan Wang, Richard Ru-Gin Chang
  • Publication number: 20210391419
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. A floating island of a second conductivity type of a cell region, a floating island of the second conductivity type of a termination region, a pillar of the second conductivity type of the cell region and a pillar of the second conductivity type of the termination region may be formed through adding a super junction mask (or reticle) after forming the epitaxial layer of a first conductivity type, through a well mask (or reticle) before or after forming a well of the second conductivity type, and through a contact mask (or reticle) before or after forming a contact structure. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Conghui LIU, Huan WANG, Longkang YANG, Richard Ru-Gin CHANG
  • Publication number: 20210391418
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) in both cell region and edge termination region and a method of making the same. A floating island of a second conductivity type of a cell region, a floating island of the second conductivity type of a termination region, a pillar of the second conductivity type of the cell region and a pillar of the second conductivity type of the termination region may be formed through adding a super junction mask (or reticle) after forming the epitaxial layer of a first conductivity type, through a well mask (or reticle) before or after forming a well of the second conductivity type, and through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Conghui LIU, Huan WANG, Longkang YANG, Richard Ru-Gin CHANG
  • Publication number: 20210391453
    Abstract: The present application provides an insulated gate bipolar transistor (IGBT) device with narrow mesa and a manufacture thereof. The device comprises: a semiconductor substrate; gate trench structures and emitter trench structures formed on front surface of the semiconductor substrate and alternately arranged along with horizontal direction; wherein the gate trench structures and the emitter trench structures are respectively set in pair along with the arrangement direction, and the pairs of the gate trench structures and the pairs of the emitter trench structures are set in alternate arrangement along with the arrangement direction; well regions formed between the emitter trench structures of one pair; emitter injection regions formed between the gate trench structures of one pair and between the emitter trench structures of one pair, respectively; and wherein, in the region between the emitter trench structures of the one pair, the emitter injection region is above the well region.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 16, 2021
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Ching-Ju LIN, Ying-Tsung WU, Conghui LIU, Longkang YANG, Huan WANG, Richard Ru-Gin CHANG
  • Publication number: 20210391416
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well region of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Conghui LIU, Huan WANG, Longkang YANG
  • Publication number: 20210391417
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Conghui LIU, Huan WANG, Longkang YANG
  • Publication number: 20210343850
    Abstract: The present invention provides a trench gate structure and a method of forming the same. The method comprises steps of forming a first trench on the surface of a substrate, a surface of a bottom of the first trench comprising a crystal face belonging to the first family of crystal faces, and a surface of a sidewall of the first trench comprising another crystal face belonging to a second family of crystal faces. With a face-selective wet etching, a specific crystal face is presented on the surface of the bottom of the trench and a thicker gate oxide layer is formed thereon after performing thermal oxidation to avoid from failure due to thinner gate oxide layer on the surface of the bottom, increase breakdown voltage, and improve reliability of the device.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 4, 2021
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Longkang YANG, Huaihua XU, Huan WANG, Richard Ru-Gin CHANG