Patents by Inventor Longxing Shi

Longxing Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11394306
    Abstract: Provided is a dynamic control method that turns off a primary-side switching transistor when an output voltage exceeds an upper limit, and control the switching of a secondary-side synchronous rectification transistor with a fixed cycle and a fixed duty cycle. During the time that the synchronous rectification transistor is turned on, the energy of a load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly and the overshoot voltage to decrease greatly.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 19, 2022
    Assignees: CSMC TECHNOLOGIES FAB2 CO., LTD., SOUTHEAST UNIVERSITY
    Inventors: Shen Xu, Wei Wang, Feng Lin, Boyong He, Wei Su, Weifeng Sun, Longxing Shi
  • Publication number: 20220223692
    Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.
    Type: Application
    Filed: September 25, 2020
    Publication date: July 14, 2022
    Applicants: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO.,LTD
    Inventors: SIYANG LIU, NINGBO LI, DEJIN WANG, KUI XIAO, CHI ZHANG, SHENG LI, XINYI TAO, WEIFENG SUN, LONGXING SHI
  • Patent number: 11367785
    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Jing Zhu, Ankang Li, Long Zhang, Weifeng Sun, Shengli Lu, Longxing Shi
  • Publication number: 20220189459
    Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 16, 2022
    Inventors: Weiwei SHAN, Lixuan ZHU, Jun YANG, Longxing SHI
  • Publication number: 20220157975
    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer.
    Type: Application
    Filed: March 31, 2020
    Publication date: May 19, 2022
    Inventors: Jing ZHU, Ankang LI, Long ZHANG, Weifeng SUN, Shengli LU, Longxing SHI
  • Patent number: 11336217
    Abstract: A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: May 17, 2022
    Assignees: CSMC TECHNOLOGIES FAB2 CO., LTD., SOUTHEAST UNIVERSITY
    Inventors: Rui Zhong, Mingshu Zhang, Sen Zhang, Jinyu Xiao, Wei Su, Weifeng Sun, Longxing Shi
  • Patent number: 11323039
    Abstract: A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a critical value Tset, calculating a time interval Ttap between adjacent zero points in the current connection time, outputting a shutdown signal at the zero points, and comparing the time interval Ttap with the preset critical value Tset; when Ttap>Tset, controlling the current shutdown time to be less than the shutdown time of the preceding cycle and outputting a start signal; when Ttap=0, controlling the current shutdown time to be greater than the shutdown time of the preceding cycle and outputting a start signal; and when 0<Ttap<=Tset, controlling the current shutdown time to be the same as the shutdown time of the preceding switch cycle and outputting a start signal.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: May 3, 2022
    Inventors: Weifeng Sun, Rongrong Tao, Hao Wang, Jinyu Xiao, Wei Su, Shen Xu, Longxing Shi
  • Patent number: 11322606
    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 3, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weifeng Sun, Siyang Liu, Sheng Li, Chi Zhang, Xinyi Tao, Ningbo Li, Longxing Shi
  • Publication number: 20220115532
    Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 14, 2022
    Inventors: Weifeng SUN, Rongcheng LOU, Kui XIAO, Feng LIN, Jiaxing WEI, Sheng LI, Siyang LIU, Shengli LU, Longxing SHI
  • Publication number: 20220085727
    Abstract: A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.
    Type: Application
    Filed: December 19, 2019
    Publication date: March 17, 2022
    Inventors: Weifeng SUN, Huaxin ZHANG, Hu ZHANG, Menglin YU, Siyu ZHAO, Shen XU, Longxing SHI
  • Publication number: 20220069718
    Abstract: Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.
    Type: Application
    Filed: June 19, 2020
    Publication date: March 3, 2022
    Inventors: Shen XU, Minggang CHEN, Wanqing YANG, Dejin WANG, Rui JIANG, Weifeng SUN, Longxing SHI
  • Publication number: 20220052613
    Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.
    Type: Application
    Filed: May 15, 2020
    Publication date: February 17, 2022
    Inventors: Shen XU, Siyu ZHAO, Congming QI, Sen ZHANG, Xiaoyu SHI, Weifeng SUN, Longxing SHI
  • Patent number: 11201557
    Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: December 14, 2021
    Assignees: CSMC TECHNOLOGIES FAB2 CO, LTD., SOUTHEAST UNIVERSITY
    Inventors: Qinsong Qian, Shengyou Xu, Feng Lin, Hao Wang, Wei Su, Qi Liu, Longxing Shi
  • Publication number: 20210336009
    Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.
    Type: Application
    Filed: September 25, 2018
    Publication date: October 28, 2021
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Weifeng SUN, Siyang LIU, Lizhi TANG, Sheng LI, Chi ZHANG, Jiaxing WEI, Shengli LU, Longxing SHI
  • Patent number: 11158708
    Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 26, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weifeng Sun, Siyang Liu, Lizhi Tang, Sheng Li, Chi Zhang, Jiaxing Wei, Shengli Lu, Longxing Shi
  • Patent number: 11152936
    Abstract: The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: October 19, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Jing Zhu, Weifeng Sun, Bowei Yang, Siyuan Yu, Yangyang Lu, Longxing Shi
  • Publication number: 20210313975
    Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 7, 2021
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Weiwei SHAN, Jun YANG, Longxing SHI
  • Patent number: 11139805
    Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 5, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weiwei Shan, Jun Yang, Longxing Shi
  • Patent number: 11081967
    Abstract: The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 3, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Qinsong Qian, Shengyou Xu, Qi Liu, Weifeng Sun, Shengli Lu, Longxing Shi
  • Publication number: 20210234030
    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
    Type: Application
    Filed: October 21, 2019
    Publication date: July 29, 2021
    Inventors: Weifeng SUN, Siyang LIU, Sheng LI, Chi ZHANG, Xinyi TAO, Ningbo LI, Longxing SHI