Patents by Inventor Longyang YU

Longyang YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956946
    Abstract: The semiconductor structure manufacturing method includes the steps of: providing a substrate with bit line contact regions and isolation regions located between adjacent bit line contact regions; forming a groove in the substrate, the bottom of the groove exposes the bit line contact region and the isolation region adjacent to the bit line contact region; forming a contact region isolation layer covering at least sidewalls of the groove; and forming a contact region to cover the contact region isolating the surface of the layer and filling the bit line contact layer of the groove, the bit line contact layer being in contact with the bit line contact region at the bottom of the groove; forming a bit line layer on the bit line contact layer. The invention avoids damage to the sidewalls of the active region in the substrate.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: ChangXin Memory Technologies, Inc.
    Inventors: Yexiao Yu, Zhongming Liu, Longyang Chen, Jia Fang
  • Publication number: 20210364555
    Abstract: The present invention provides a current detection circuit applied to a SiC field effect transistor. The current detection circuit includes a current detection loop and an acquisition loop on the current detection loop. The current detection loop includes a voltage source, a capacitor, a first SiC field effect transistor, a second SiC field effect transistor, and a sampling resistor. The first SiC field effect transistor is connected to a power signal. The second SiC field effect transistor is connected to a pulse signal. The acquisition loop includes a compensating resistor and a compensating inductor. The compensating resistor and the compensating inductor are connected in series and then connected in parallel at two ends of the sampling resistor to counteract the influence of total parasitic inductance in the current detection loop.
    Type: Application
    Filed: April 1, 2021
    Publication date: November 25, 2021
    Inventors: Laili WANG, Chengzi YANG, Huaqing LI, Xingshuo LIU, Longyang YU, Yunqing PEI, Yongmei GAN, Xu YANG