Abstract: A computer system that installs in the proximity of the vehicle's operator by attaching to the vehicle's wiring harness (e.g., via a power outlet in the vehicle cabin). The device, gathers data relating to the operational state of the vehicle's battery, calculates various health information of the battery from the gathered data, and provides the health and operational state of the battery to the vehicle's operator. To facilitate battery health calculations, the device receives input from a temperature sensor that is remote to the battery, such as a temperature sensor in the device's housing or in the vehicle cabin. The temperature reading can be used to approximate the temperature of the battery. The computer system can also support non-battery related functions, such as navigation, theft deterrence, etc. Algorithms utilizing battery health data over multiple load cycles to determine the health of a battery are also disclosed.

Abstract: A computer array 100 including a field of processors 101-124 each processor having a separate memory. The processors 101-124 are connected to their immediate neighbors with links 200. Several configurations of the links are described including differing types of data lines 210 and control lines 215. Along lines 215 Process Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors 101-124 to provide a method for altering the mode of hybrid processors 107-118 in the array.

Abstract: A ring oscillator comprises a control circuit for receiving a frequency-selection signal operative to select from at least two ring oscillator frequencies, said control circuit using said control signal to generate a first control signal and a second control signal; a primary chain of an odd number of serially connected NOT gates, said primary chain including a primary switching NOT gate responsive to the first control signal and operative to perform a logical NOT or an IGNORE function on a first oscillating input signal to generate a first output signal; and a secondary chain of serially connected NOT gates, said secondary chain logically parallel to at least said primary switching NOT gate, said secondary chain including a secondary switching NOT gate responsive to the second control signal and operative to perform a logical NOT or an IGNORE function on a second oscillating input signal to generate a second output signal.

Abstract: A computer array 100 including a field of processors 101-124 each processor having a separate memory. The processors 101-124 are connected to their immediate neighbors with links 200. Several configurations of the links are described including differing types of data lines 210 and control lines 215. Along lines 215 Process Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors 101-124 to provide a method for altering the mode of hybrid processors 107-118 in the array.

Abstract: A ring oscillator comprises a control circuit for receiving a frequency-selection signal operative to select from at least two ring oscillator frequencies, said control circuit using said control signal to generate a first control signal and a second control signal; a primary chain of an odd number of serially connected NOT gates, said primary chain including a primary switching NOT gate responsive to the first control signal and operative to perform a logical NOT or an IGNORE function on a first oscillating input signal to generate a first output signal; and a secondary chain of serially connected NOT gates, said secondary chain logically parallel to at least said primary switching NOT gate, said secondary chain including a secondary switching NOT gate responsive to the second control signal and operative to perform a logical NOT or an IGNORE function on a second oscillating input signal to generate a second output signal.

Abstract: Among the embodiments of the present invention is a technique that includes executing a first protocol on test bus (40) in accordance with an established test standard to operate a first topology of several test ports (70) and activating to a shadow controller (60) by executing a second protocol on test bus (40). Operation of the test ports (70) is suspended during execution of the second protocol. During activation, the shadow controller (60) can be used to set-up a second topology of one or more of test ports (70) for operation after the test port suspension is discontinued.

Abstract: An array boundary checking method is disclosed for providing hardware based array boundary checking in a Java environment. During the first machine cycle of a current array access command, an array reference value is loaded into a system-data address controller and an array boundary checker. Next, during the second machine cycle of the current array access command, an array index value is written to the system-data address controller and the array boundary checker. Also during the second machine cycle of the current array access command, a maximum array index value is read from the Java array and written to the array boundary checker. The array boundary checker utilizes these values to determine the validity of the current array access command. Finally, during the third machine cycle an array value is accessed in memory. In the present invention the array value is only accessed when the current array access command is valid.

Abstract: A power management method is disclosed which provides power management for a hardware based Java accelerator. Initially, a Java mode signal is provided from a host processor in response to initiating a Java application. Thereafter, power to the host processor is reduced, and power to a Java processor is increased in response to the Java mode signal. Then, when execution of the Java application halts, a Java completion signal is generated from the Java processor, thus signaling the system to return control back to the host processor.

Abstract: Various enhancements may be made to a DMA controller to optimize the DMA controller for use in non-uniform DMA applications such as Universal Serial Bus (USB) applications. First, a DMA count register that is used to store a count value that controls the length of a data transfer over a DMA channel may be capable of being selectively disabled, such that when the DMA count register is disabled, a DMA control circuit may perform a data transfer independent of the DMA count register. An endpoint watchdog timer may also be coupled to a DMA control circuit and configured to generate an interrupt if no data is received by the DMA channel within a predetermined period of time. In addition, a DMA control circuit may incorporate partial word hold off functionality to delay transmission of a final word of data from a data packet if the final word is a partial word.

Abstract: A method and apparatus for supporting a host computer system in executing a JAVA computer program. An auxiliary system, including multiple non-host processors, coupled to a non-host memory, via a bus to the host computer system, interfaces with a JAVA Virtual Machine (JVM) to execute one or more threads of the JAVA computer program. The JVM can be instantiated in the non-host memory. The JVM performs allocation of an additional non-host processor for interfacing with the JVM to execute the new thread. The auxiliary system need not be a permanent part of the host computer system. In one embodiment the auxiliary system is coupled to the host computer system to run JAVA programs. The auxiliary system can be detached from the host computer system or can be implemented as a permanent part of the host computer system.

Abstract: Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer register (52b) having a common register name. Processor (22) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register (52a) under a first condition and with stack pointer register (52b) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Abstract: Among the embodiments of the present invention is test equipment (440) to test an integrated circuit (420). The integrated circuit (420) includes one or more processors and one or more communication devices (130). The test equipment (440) includes a responder integrated circuit (450) that has at least one processor, several communication devices (160), and one or more configuration connections (192). The responder integrated circuit responds to commands from the first integrated circuit (420) and a configuration established with the one or more configuration connections (192) to test operation of the one or more communication devices (130).

Abstract: Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer register (52b) having a common register name. Processor (22) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register (52a) under a first condition and with stack pointer register (52b) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Abstract: A hybrid one time pad encryption and decryption apparatus with methods for encrypting and decrypting data wherein a one time random number pad provides high security encryption. The random number sequence is encrypted using DES, RSA or other technique and embedded in the message as a function of the random pad itself. This generates an encryption message that is impervious to attempts to directly decode the message text as the message is randomly dispersed throughout a message and the message contains as much quasi-random data as text. The message is also relatively impervious to attempts to decode the cipher, as the cipher is randomly interrupted by the encrypted data.

Abstract: A cryptographic device includes a de-multiplexer, a plurality of encryption blocks, a plurality of permutation blocks, and a multiplexer. The encryption blocks encrypt data to produce encrypted data. The de-multiplexer receives data portions from a plaintext message and directs the data portions to one of the encryption blocks, based on a value within a path control session key. Each permutation block is associated with an encryption block. Each permutation block permutes encrypted data from the encryption block associated therewith. The multiplexer receives data portions from each of the plurality of permutation blocks to produce an encrypted output data stream.

Abstract: A method for simultaneously generating one time pads and an apparatus which implements the method to produce a secure encryption system. The method and apparatus use the Diffie-Hellman key exchange algorithm to produce a one time pad rather than exchange keys. This makes it practical to generate one time pads for use in secure transmissions.

Abstract: A method and apparatus for managing power consumption in a computer system wherein the method and apparatus is compliant with the proposed Advanced Configuration and Power Interface (ACPI) specification. In one embodiment, a power management processor is sandwiched between platform hardware and the ACPI register layer. The processor processes all operating power management commands and requests while remaining transparent to the user and the operating system. In so doing, routine power management functions, so classified by the operating system, are implemented by the operating system. Sophisticated power management features, on the other hand, are implemented by the present invention independent from operating system control. Accordingly, in the present invention, the operating system need not suspend processing of other threads to process sophisticated power management procedures.

Abstract: A method and system of detecting objects displayed on a display screen is described. Each object displayed on the screen visually emits a unique identification signal. The identification signal or lack of an identification signal is detected by a detector such as a light pen or video gun and the detector transmits the identification signal on a serial bus to the display screen graphics controller thereby indicating to the controller the position on the screen at which the detector is pointed.

Abstract: A method and system for detecting objects displayed on a display screen is described. Each object displayed on the screen visually emits a unique identification signal in the form of a color signal having multiple color components. The relative peak amplitude of each color component in the color signal is detected by sampling the color signal with photo-sensors corresponding to each color component. The sampled color components are digitized and transmitted to the display screen graphics controller thereby indicating to the controller the object on the screen at which the detector is pointed.

Abstract: A keyboard controller for a computer system with integrated Real Time Clock (RTC) functionality. The keyboard controller has a microprocessor for controlling peripheral device bus traffic such as keyboard and mouse traffic. The microprocessor also acts as a boot device for the computer system. By programming the microprocessor to emulate RTC functions, adding a divider circuit, and having an I/O support block which stores RTC registers and an extended CMOS RAM memory block, the entire RTC FSB along with its power detection and switching circuit can be removed.