Patents by Inventor Lonnie L. Lambert

Lonnie L. Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for improved memory scan testability
    Patent number: 7315971
    Abstract: A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: January 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: William E. Grose, Lonnie L. Lambert, Jeanne Krayer Pitz, Toru Tanaka