Patents by Inventor Loren B. Reiss
Loren B. Reiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11238204Abstract: Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.Type: GrantFiled: October 8, 2020Date of Patent: February 1, 2022Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Loren B. Reiss, Fred Staples Stivers, Steven Martin Broome
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Patent number: 11228416Abstract: Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.Type: GrantFiled: July 30, 2020Date of Patent: January 18, 2022Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Loren B. Reiss, Christopher George Moscone, James Dennis Vandersand, Jr.
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Patent number: 11190331Abstract: A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.Type: GrantFiled: December 16, 2020Date of Patent: November 30, 2021Assignee: Cadence Design Systems, Inc.Inventors: Loren B. Reiss, Scott David Huss, Fred Staples Stivers, James Dennis Vandersand, Jr.
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Patent number: 11165553Abstract: A phase interpolator of a physical layer (PHY) device comprise a phase interpolator to generate a set of asynchronous sampler clocks. A sampler of the PHY device samples a calibration data pattern using a first sampler clock from the set of asynchronous sampler clocks. A calibration control component of the PHY device detects a misalignment of a phase relationship among the set of asynchronous sampler clocks based on the sampled data. In response to detecting the misalignment, the calibration control component calibrates the first sampler clock using a second sampler clock and a third sampler clock.Type: GrantFiled: September 11, 2020Date of Patent: November 2, 2021Assignee: Cadence Design Systems, Inc.Inventors: Loren B. Reiss, Scott David Huss, Christopher George Moscone
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Patent number: 11133793Abstract: Various embodiments provide for phase interpolators with phase adjusters to provide step resolution, which can be used with a circuit such as a data serializer/deserializer circuit. In particular, for some embodiments, a phase interpolator is coupled to a phase adjuster, where the combination of the phase interpolator and the phase adjuster is configured to interpolate between phases in phase adjustment steps at a phase adjustment step resolution. For such embodiments, the phase adjustment step resolution of the steps is achieved by controlling the phase interpolator and the phase adjuster.Type: GrantFiled: December 1, 2020Date of Patent: September 28, 2021Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Loren B. Reiss, Christopher George Moscone, Kelvin E. McCollough
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Patent number: 11108425Abstract: A calibration control component within a transmit (TX) or receive (RX) device executes a calibration sequence to ensure reliable data transmission and reception within the device. The calibration sequence comprises a set of calibration functions that are sequentially executed. The calibration control component detects a pause function being enabled based on a pause function configuration register. Based on detecting the pause function being enabled, the calibration control component pauses execution of the calibration sequence.Type: GrantFiled: August 27, 2020Date of Patent: August 31, 2021Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Loren B. Reiss, Fred Staples Stivers, Matthew Robert Collin, James Lee House, Ramakrishna Kasukurthi
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Patent number: 10992449Abstract: A set of encoders within a transmitter (TX) physical layer (PHY) encode incoming data using a predefined encoder scheme by translating multiple data segments into a set of balanced bit sequences. Each data segment comprises a first number of bits and each balanced bit sequence comprises a second number of bits. A data striping component distributes the set of balanced bit sequences to a set of serializers by routing bits from particular bit positions in each balanced bit sequence to a corresponding serializer. The set of serializers generates serialized data based on the set of balanced bit sequences.Type: GrantFiled: July 27, 2020Date of Patent: April 27, 2021Assignee: Cadence Design Systems, Inc.Inventors: Loren B. Reiss, Fred Staples Stivers, Eric Harris Naviasky
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Patent number: 6775763Abstract: A circuit arrangement and method facilitate the execution of switch instructions such as Java lookupswitch and tableswitch instructions in hardware through emulation of such instructions using a plurality of conditional branch instructions from the same instruction set as the switch instructions, and which are capable of being directly implemented in hardware. The conditional branch instructions are typically generated by switch instruction handling logic and passed to execution logic capable of natively executing the conditional branch instructions. By emulating a complex switch instruction in switch instruction handling logic using a plurality of conditional branch instructions from the same instruction set, often the amount of custom circuitry needed to fully support a complex switch instruction is substantially reduced from what would be required to natively support the switch instruction in the execution logic of a hardware processor.Type: GrantFiled: March 9, 2001Date of Patent: August 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Bonnie C. Sexton, Loren B. Reiss
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Patent number: 6658508Abstract: An expansion module for a Handspring Visor includes a multi-master AMBA Advanced System Bus (ASB). The Springboard bus of the visor is coupled to the ASB bus via Springboard-to-ASB-bus bridge. This bridge includes a protocol translator and a second Arm7 to ASB interface. The protocol translator translates bi-directionally between the Springboard bus protocol and the Arm7TDMI protocol. The translator includes an interface to the Springboard bus and a state machine. The state machine coordinates data transfers between the buses. The state machine also monitors signals indicating when each of the buses begins to treat a data transfer as complete so that the data transfer can be validated or flagged as an error condition. A programmable counter adjusts maximum counts to compensate for different clock frequencies in measuring a write-wait state duration to ensure valid writes from the Visor to the ASB bus.Type: GrantFiled: January 31, 2000Date of Patent: December 2, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Loren B. Reiss, Bonnie C. Sexton, D. Adam Shiel, R. Christopher Noonan
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Patent number: 6571308Abstract: An expansion module for a Handspring Visor (which conforms to the Springboard bus specification) includes a multi-master AMBA Advanced System Bus (ASB). Optionally, an Arm7 processor is attached to this bus via an Arm7 to ASB interface as one master. The Springboard bus of the visor is coupled to the ASB bus via a Springboard-to-ASB-bus bridge. This bridge comprises a protocol translator and a second Arm7 to ASB interface. The protocol translator translates bi-directionally between the Springboard bus protocol and the Arm7TDMI protocol. The translator includes an interface to the Springboard bus and a state machine. The state machine coordinates data transfers between the buses. The state machine also monitors signals indicating when each of said buses begins to treat a data transfer as complete so that the data transfer can be validated or flagged as an error condition.Type: GrantFiled: January 31, 2000Date of Patent: May 27, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Loren B. Reiss, Bonnie C. Sexton, D. Adam Shiel
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Publication number: 20020184479Abstract: A circuit arrangement and method facilitate the execution of switch instructions such as Java lookupswitch and tableswitch instructions in hardware through emulation of such instructions using a plurality of conditional branch instructions from the same instruction set as the switch instructions, and which are capable of being directly implemented in hardware. The conditional branch instructions are typically generated by switch instruction handling logic and passed to execution logic capable of natively executing the conditional branch instructions. By emulating a complex switch instruction in switch instruction handling logic using a plurality of conditional branch instructions from the same instruction set, often the amount of custom circuitry needed to fully support a complex switch instruction is substantially reduced from what would be required to natively support the switch instruction in the execution logic of a hardware processor.Type: ApplicationFiled: March 9, 2001Publication date: December 5, 2002Applicant: Koninklijke Philips Electronics N.V.Inventors: Bonnie C. Sexton, Loren B. Reiss
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Patent number: 6477609Abstract: An expansion module for a Handspring Visor (which conforms to the Springboard bus specification) includes a multi-master AMBA Advanced System Bus (ASB). Optionally, an Arm7 processor is attached to this bus via an Arm7 to ASB interface as one master. The Springboard bus of the visor is coupled to the ASB bus via a Springboard-to-ASB-bus bridge. This bridge comprises a protocol translator and a second Arm7 to ASB interface. The protocol translator translates bi-directionally between the Springboard bus protocol and the Arm7TDMI protocol. The translator includes an interface to the Springboard bus and a state machine. The state machine coordinates data transfers between the buses. The state machine also monitors signals indicating when each of said buses begins to treat a data transfer as complete so that the data transfer can be validated or flagged as an error condition.Type: GrantFiled: January 31, 2000Date of Patent: November 5, 2002Assignee: Koninklijke Philips Electronics N.V.Inventors: Loren B. Reiss, Bonnie C. Sexton, D. Adam Shiel