Abstract: Systems and methods disclosed herein provide for preventing the mis-equalization of signals transmitted over short transmission channels. Embodiments of the systems and methods provide for a receiver including a digital receiver equalization circuit that selectively provides a correction signal to a DFE tap weight based on the value of the current DFE tap weight as well as the logical values of the in-phase and error data samples associated with received signal.

Abstract: A circuit and method for adaptively controlling an equalizer circuit to reduce intersymbol interference at low frequencies relative to a transmit frequency of an input signal from a transmitter. The input signal is converted into a data signal by a receiver. At least one delayed data signal is formed by delaying the data signal by at least one unit interval (UI) beyond a length of a decision feedback equalizer (DFE) in the receiver. An error signal is formed by comparing the input signal to a threshold value. An error signal sample is correlated with at least one delayed data signal sample to determine whether to adjust a control coefficient of the equalizer. Thus the equalizer is controlled as if the DFE had at least one additional tap.

Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include operatively connecting one or more lane modules of an integrated circuit (IC) to form one or more links. The method may further include associating a FIFO reset generator with each of the one or more lane modules and receiving a signal from the FIFO reset generator at a synchronization FIFO. The method may also include aligning, at the synchronization FIFO, one or more enqueue pointers and dequeue pointers.

Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween. The method may further include resetting each link independently using the one or more lane modules.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A method and system are provided for increasing processing efficiency associated with data frames transiting a network node having multiple ports. The method and system accomplish their objects via the following. A data frame having a header and data is received. An associated pointer for at least one portion of the received data frame is provided. The associated pointer is provided by segmenting each received data frame into parts, and associating with each segmented part a pointer. Thereafter, a portion of the received data frame is modified independent of other portions of the received data frame via utilization of given one or more of the associated pointers. Additionally, one or more copies of a portion (which can include the whole) of the received data frame is constructed by recalling each segmented part associated with one or more selected ones of the associated pointers. Furthermore, a determination is made as to whether the received header indicates unicast or multicast.

Abstract: A system for coupling a local area network to a wide area network utilizes a PCI (Peripheral Component Interface) bus to couple a PCI interface to a PCI network interface card, which is coupled to the wide area network. The wide area network could be an asynchronous transfer mode network or a high bandwidth ethernet. If the PCI network interface card operates as a PCI master, then the PCI interface will operate as a PCI slave. If the PCI network interface card operates as a PCI slave, then the PCI interface of the invention will operate as a PCI master.

Abstract: A method and system are provided for enabling simultaneous cut-through and store-and-forward transmission of frames in high speed network devices. A Buffer Parameter Vector chains multiple frame buffers together. Frame Parameter Vectors created for each unique version of a frame are used to manage frames as they flow through the network device. Cut-through/store-and-forward decision logic determines whether frames can be transmitted by cut-through or store-and-forward. Multiple unique frames or copies of a frame that are to be transmitted store-and-forward have their Frame Parameter Vectors chained together by pointers. The cut-through/store-and-forward decision logic steps through the chain of Frame Parameter Vectors resulting in the frames associated with each Frame Parameter Vector being transmitted.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A method and system are provided for traffic shaping and bandwidth scaling in a high speed internetworking device. A slot time wheel mechanism is provided for traffic rate control and a credit/debit mechanism is provided for traffic shaping and scaling. The high speed traffic scaler and shaper incorporates a programmable slot time wheel, a traffic scaler state machine, a traffic shaper parameter table and a traffic scaler processor. The traffic scaler processor incorporates a traffic queue allocation manager, a queue priority arbiter, a port enable selector, a port priority arbiter and a DMA channel arbiter. The traffic queue allocation manager and the queue priority, port priority and DMA channel arbiters are each controlled by a corresponding state machine. The parameters in the traffic shaper parameter table are dynamically updated for each logical queue and are used to enable the credit/debit mechanism.

Abstract: A sequence in which two or more of the data units enter the network node, via a specific one of the multiple ports, is recorded. And, the two or more of the data units are transmitted from the network node according to the recorded sequence. The method and system achieve the recording of sequence via the following. In response to an insertion of one of the two or more data units into a specific one of the multiple processor subsystems, the specific one of the multiple processor subsystems is associated with a specific one of the multiple ports by which the one of the two or more data units entered the network node, and any other of the multiple processor subsystems that are currently processing on any other of the two or more data units that entered the network node through the specific one of the multiple ports is noted.

Abstract: A method for improving the performance of an existing busoriented computer system with minimum or no design change to the existing hardware, bus protocol, or bus operation is disclosed. Specifically, the present invention improves the effective bandwidth of an existing bus architecture by creating multiple physical instantiations of the existing bus and directing traffic onto these different buses based on the type of bus operation being performed. This results in multiple components having the capability to simultaneously perform bus operations, therefore improving the effective bandwidth of the system. This invention also allows the components which are current being utilized in the existing bus architecture to be re-utilized with minimum additional external logic.