Patents by Inventor Loren C. Wilton

Loren C. Wilton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11300992
    Abstract: Methods and systems for implementing independent time in a hosted operating environment are disclosed. The hosted, or guest, operating environment, can be seeded with a guest time value by a guest operating environment manager that maintains a time delta between a host clock time and an enterprise time. The guest operating environment can subsequently manage its guest clock from the guest time value. If the guest operating environment is halted, the guest operating environment manager can manage correspondence between the host clock time and the enterprise time by periodically assessing divergence between actual and expected values of the host clock time.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: April 12, 2022
    Assignee: Unisys Corporation
    Inventors: Robert F. Inforzato, Dwayne E. Ebersole, Daryl R. Smith, Grace W. Lin, Andrew Ward Beale, Loren C. Wilton
  • Publication number: 20210072786
    Abstract: Methods and systems for implementing independent time in a hosted operating environment are disclosed. The hosted, or guest, operating environment, can be seeded with a guest time value by a guest operating environment manager that maintains a time delta between a host clock time and an enterprise time. The guest operating environment can subsequently manage its guest clock from the guest time value. If the guest operating environment is halted, the guest operating environment manager can manage correspondence between the host clock time and the enterprise time by periodically assessing divergence between actual and expected values of the host clock time.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 11, 2021
    Inventors: ROBERT F. INFORZATO, DWAYNE E. EBERSOLE, DARYL R. SMITH, GRACE W. LIN, ANDREW WARD BEALE, LOREN C. WILTON
  • Patent number: 8898642
    Abstract: Methods and systems are disclosed for analyzing performance of a translated code stream executing within a central processing module. One method includes, during execution of one or more native instructions corresponding to each non-native operator in the code stream by the code execution unit, counting the occurrence of the non-native operator, determining a duration of execution of the one or more native instructions, and adding the non-native operator to a trace sequence. The method also includes, after execution of the code stream within the central processing module, generating a data file of non-native operators executed within the code stream, the data file of operators including a name of each non-native operator, an elapsed amount of time within the code execution unit that the one or more native operators corresponding to the non-native operator are executed, and a number of occurrences of the non-native operator within the code stream.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: November 25, 2014
    Assignee: Unisys Corporation
    Inventors: Andrew Ward Beale, Loren C. Wilton
  • Patent number: 8527969
    Abstract: Various embodiments of systems and methods for dynamic binary translation in an interpreter are disclosed. An embodiment comprises a method for dynamic binary translation in an interpreter.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: September 3, 2013
    Assignee: Unisys Corporation
    Inventors: Robert Joseph Meyers, Andrew Ward Beale, Loren C. Wilton
  • Publication number: 20130219370
    Abstract: Methods and systems are disclosed for analyzing performance of a translated code stream executing within a central processing module. One method includes, during execution of one or more native instructions corresponding to each non-native operator in the code stream by the code execution unit, counting the occurrence of the non-native operator, determining a duration of execution of the one or more native instructions, and adding the non-native operator to a trace sequence. The method also includes, after execution of the code stream within the central processing module, generating a data file of non-native operators executed within the code stream, the data file of operators including a name of each non-native operator, an elapsed amount of time within the code execution unit that the one or more native operators corresponding to the non-native operator are executed, and a number of occurrences of the non-native operator within the code stream.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Inventors: Andrew Ward Beale, Loren C. Wilton
  • Patent number: 8276128
    Abstract: Various embodiments of systems and methods for dynamic binary translation in an interpreter are disclosed. An embodiment comprises a method for dynamic binary translation in an interpreter.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: September 25, 2012
    Assignee: Unisys Corporation
    Inventors: Andrew Ward Beale, Robert Joseph Meyers, Loren C. Wilton
  • Publication number: 20110016458
    Abstract: Various embodiments of systems and methods for dynamic binary translation in an interpreter are disclosed. An embodiment comprises a method for dynamic binary translation in an interpreter.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Inventors: Andrew Ward Beale, Robert Joseph Meyers, Loren C. Wilton
  • Publication number: 20110016459
    Abstract: Various embodiments of systems and methods for dynamic binary translation in an interpreter are disclosed. An embodiment comprises a method for dynamic binary translation in an interpreter.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Inventors: Robert Joseph Meyers, Andrew Ward Beale, Loren C. Wilton
  • Patent number: 5794011
    Abstract: A performance regulator program monitors and controls in real time, the performance level which an application program achieves when it is executed on a digital computer. With this performance regulator program, any external units which are coupled to the computer are prevented from being overloaded by excessive performance in the application program. Also with this performance regulator program, several models of the application program can be easily generated such that each model achieves a different performance level.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: August 11, 1998
    Assignee: Unisys Corporation
    Inventors: Derek William Paul, Loren C. Wilton, Frederick Joseph Barker