Patents by Inventor Loren Chow

Loren Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby
    Patent number: 9711591
    Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Matthew V. Metz, James M. Powers, Van H. Le, Benjamin Chu-Kung, Mark R. Lemay, Marko Radosavljevic, Niti Goel, Loren Chow, Peter G. Tolchinsky, Jack T. Kavalieros, Robert S. Chau
  • Depositing polar materials on non-polar semiconductor substrates
    Publication number: 20070238281
    Abstract: Lattice mismatch and polar to non-polar issues may lead to dislocations and other defects between silicon or germanium substrates and group III-V materials such as indium antimonide. The provision of lattice matching layers and buffer layers may enable these defects to be reduced.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 11, 2007
    Inventors: Mantu Hudait, Mohamad Shaheen, Loren Chow, Peter Tolchinsky, Joel Fastenau, Dmitri Loubychev, Amy Liu, Suman Datta, Jack Kavalieros, Robert Chau
  • III-V and II-VI compounds as template materials for growing germanium containing film on silicon
    Patent number: 7202503
    Abstract: An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III–V elements and a combination of II–VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Loren Chow, Mohamad Shaheen
  • III-V and II-VI compounds as template materials for growing germanium containing film on silicon
    Publication number: 20060001018
    Abstract: An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III-V elements and a combination of II-VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Loren Chow, Mohamad Shaheen