Patents by Inventor Loren J. Swenson
Loren J. Swenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240151782Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.Type: ApplicationFiled: November 22, 2023Publication date: May 9, 2024Inventors: Loren J. Swenson, Emile M. Hoskinson, Mark H. Volkmann, Andrew J. Berley, George E.G. Sterling, Jed D. Whittaker
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Publication number: 20240138268Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material.Type: ApplicationFiled: February 17, 2022Publication date: April 25, 2024Inventors: Colin C. Enderud, Mohammad H. Amin, Loren J. Swenson
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Patent number: 11957065Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.Type: GrantFiled: May 17, 2021Date of Patent: April 9, 2024Assignee: 1372934 B.C. LTD.Inventors: Shuiyuan Huang, Byong H. Oh, Douglas P. Stadtler, Edward G. Sterpka, Paul I. Bunyk, Jed D. Whittaker, Fabio Altomare, Richard G. Harris, Colin C. Enderud, Loren J. Swenson, Nicolas C. Ladizinsky, Jason J. Yao, Eric G. Ladizinsky
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Patent number: 11941486Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.Type: GrantFiled: April 20, 2023Date of Patent: March 26, 2024Assignee: D-WAVE SYSTEMS INC.Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T. E. Wilkinson, Trevor Michael Lanting
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Patent number: 11879950Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.Type: GrantFiled: May 16, 2019Date of Patent: January 23, 2024Assignee: D-WAVE SYSTEMS INC.Inventors: Loren J. Swenson, Emile M. Hoskinson, Mark H. Volkmann, Andrew J. Berkley, George E. G. Sterling, Jed D. Whittaker
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Patent number: 11874344Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.Type: GrantFiled: December 15, 2022Date of Patent: January 16, 2024Assignee: D-WAVE SYSTEMS INC.Inventors: Loren J. Swenson, Andrew J. Berkley, Mark H. Volkmann, George E. G. Sterling, Jed D. Whittaker
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Patent number: 11847534Abstract: A superconducting readout system employing a microwave transmission line, and a microwave superconducting resonator communicatively coupled to the microwave transmission line, and including a superconducting quantum interference device (SQUID), may be advantageously calibrated at least in part by measuring a resonant frequency of the microwave superconducting resonator in response to a flux bias applied to the SQUID, measuring a sensitivity of the resonant frequency in response to the flux bias, and selecting an operating frequency and a sensitivity of the microwave superconducting resonator based at least in part on a variation of the resonant frequency as a function of the flux bias. The flux bias may be applied to the SQUID by an interface inductively coupled to the SQUID. Calibration of the superconducting readout system may also include determining at least one of a propagation delay, a microwave transmission line delay, and a microwave transmission line phase offset.Type: GrantFiled: August 22, 2019Date of Patent: December 19, 2023Assignee: D-WAVE SYSTEMS INC.Inventors: Jed D. Whittaker, Loren J. Swenson, Ilya V. Perminov, Abraham J. Evert, Peter D. Spear, Mark H. Volkmann, Catia Baron Aznar, Michael S. Babcock
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Patent number: 11839164Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.Type: GrantFiled: August 18, 2020Date of Patent: December 5, 2023Assignee: D-WAVE SYSTEMS INC.Inventors: Loren J. Swenson, George E. G. Sterling, Christopher B. Rich
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Publication number: 20230325695Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.Type: ApplicationFiled: April 20, 2023Publication date: October 12, 2023Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T.E. Wilkinson, Trevor Michael Lanting
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Patent number: 11730066Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures.Type: GrantFiled: August 11, 2021Date of Patent: August 15, 2023Assignee: 1372934 B.C. LTD.Inventors: Mark W. Johnson, Paul I. Bunyk, Andrew J. Berkley, Richard G. Harris, Kelly T. R. Boothby, Loren J. Swenson, Emile M. Hoskinson, Christopher B. Rich, Jan E. S. Johansson
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Publication number: 20230204691Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.Type: ApplicationFiled: December 15, 2022Publication date: June 29, 2023Inventors: Loren J. Swenson, Andrew J. Berkley, Mark H. Volkmann, George E.G. Sterling, Jed D. Whittaker
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Publication number: 20230189665Abstract: Superconducting integrated circuits and methods of forming these circuits are discussed. One superconducting integrated circuit has a substrate and a control device formed by a layer of high kinetic inductance material overlying the substrate. The control device has a loop of material, electrical connections between the loop of material and a power line, a coupling element connected to the loop of material, a pair of Josephson junctions that interrupt the loop of material, and an energy storage element connected to the loop of material. An alternative superconducting integrated circuit has a kinetic inductance device formed in a high kinetic inductance layer. The device has a compound Josephson junction structure with two parallel current paths with respective Josephson junctions, a loop of material connected to the compound Josephson junction structure, and a coupling structure. The circuit also has an additional device that couples to the coupling structure.Type: ApplicationFiled: May 7, 2021Publication date: June 15, 2023Inventor: Loren J. Swenson
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Patent number: 11663512Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.Type: GrantFiled: January 26, 2022Date of Patent: May 30, 2023Assignee: D-WAVE SYSTEMS INC.Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T. E. Wilkinson, Trevor Michael Lanting
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Publication number: 20230143506Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures.Type: ApplicationFiled: August 11, 2021Publication date: May 11, 2023Inventors: Mark W. Johnson, Paul I. Bunyk, Andrew J. Berkley, Richard G. Harris, Kelly T. R. Boothby, Loren J. Swenson, Emile M. Hoskinson, Christopher B. Rich, Jan E. S. Johansson
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Patent number: 11561269Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.Type: GrantFiled: July 29, 2021Date of Patent: January 24, 2023Assignee: D-WAVE SYSTEMS INC.Inventors: Loren J. Swenson, Andrew J. Berkley, Mark H. Volkmann, George E. G. Sterling, Jed D. Whittaker
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Publication number: 20230006324Abstract: A superconducting circuit may include a transmission line having at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. The transmission line inductance may have a value selected to at least partially compensate for a variation in a characteristic impedance of the transmission line, the variation caused at least in part by the coupling capacitance. The coupling capacitance may be distributed along the length of the transmission line. A superconducting circuit may include a transmission line having at least one transmission line capacitance, a superconducting resonator, and a coupling inductance that communicatively couples the superconducting resonator to the transmission line. The transmission line capacitance may be selected to at least partially compensate for a variation in coupling strength between the superconducting resonator and the transmission line.Type: ApplicationFiled: July 12, 2022Publication date: January 5, 2023Inventors: Jed D. Whittaker, Loren J. Swenson, Mark H. Volkmann
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Patent number: 11424521Abstract: A superconducting circuit may include a transmission line having at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. The transmission line inductance may have a value selected to at least partially compensate for a variation in a characteristic impedance of the transmission line, the variation caused at least in part by the coupling capacitance. The coupling capacitance may be distributed along the length of the transmission line. A superconducting circuit may include a transmission line having at least one transmission line capacitance, a superconducting resonator, and a coupling inductance that communicatively couples the superconducting resonator to the transmission line. The transmission line capacitance may be selected to at least partially compensate for a variation in coupling strength between the superconducting resonator and the transmission line.Type: GrantFiled: February 20, 2019Date of Patent: August 23, 2022Assignee: D-WAVE SYSTEMS INC.Inventors: Jed D. Whittaker, Loren J. Swenson, Mark H. Volkmann
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Publication number: 20220222558Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.Type: ApplicationFiled: January 26, 2022Publication date: July 14, 2022Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T.E. Wilkinson, Trevor Michael Lanting
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Publication number: 20220123048Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.Type: ApplicationFiled: February 13, 2020Publication date: April 21, 2022Inventors: Loren J. Swenson, George E.G. Sterling, Mark H. Volkmann, Colin C. Enderud
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Patent number: 11263547Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.Type: GrantFiled: January 26, 2018Date of Patent: March 1, 2022Assignee: D-WAVE SYSTEMS INC.Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T. E. Wilkinson, Trevor Michael Lanting