Patents by Inventor Loren J. Swenson

Loren J. Swenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12373167
    Abstract: A filter multiplexer for variable bandwidth annealing selection is described. The filter multiplexer has multiple pathways, where each pathway comprises a switch and a filter. Each filter has a different cutoff frequency from the other filters. Switches may be cryogenic switches. Each pathway may be communicatively coupled to an external annealing line. Upon receiving a problem, an annealing bandwidth can be selected, set or configured via the multiplexer to operate a quantum processor with a desired annealing schedule. The multiplexer may be used for calibration of a quantum processor by performing a calibration with a large annealing bandwidth, then calibrating the quantum processor by iterating through all available annealing bandwidths from the multiplexer.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: July 29, 2025
    Assignee: 1372934 B.C. LTD.
    Inventor: Loren J. Swenson
  • Publication number: 20250180673
    Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.
    Type: Application
    Filed: December 9, 2024
    Publication date: June 5, 2025
    Inventors: Loren J. Swenson, Emile M. Hoskinson, Mark H. Volkmann, Andrew J. Berkley, George E.G. Sterling, Jed D. Whittaker
  • Patent number: 12248849
    Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
    Type: Grant
    Filed: February 16, 2024
    Date of Patent: March 11, 2025
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T. E. Wilkinson, Trevor Michael Lanting
  • Publication number: 20250055457
    Abstract: A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.
    Type: Application
    Filed: December 14, 2022
    Publication date: February 13, 2025
    Inventors: Jed D. Whittaker, Mark H. Volkmann, Andrew J. Berkley, Reza Molavi, Paul Bunyk, Loren J. Swenson
  • Publication number: 20250038722
    Abstract: In an implementation, a tunable traveling wave parametric amplifier (TWPA) includes a T-stage that includes a first DC-SQUID and a first interface inductively communicatively coupled to the first DC SQUID operable to apply a first bias to the first DC SQUID. The T-stage also includes a second DC-SQUID electrically communicatively coupled to the first DC-SQUID in series via a center node, and a second interface inductively communicatively coupled to the second DC-SQUID operable to apply a second bias to the second DC-SQUID. The TWPA also includes a shunting resonator communicatively coupled to the center node via a coupling capacitance. The shunting resonator includes a third DC-SQUID, and a third interface inductively communicatively coupled to the third DC SQUID operable to apply a third bias to the third DC SQUID. The first, second, and third biases are adjustable to improve a bandwidth of the tunable TWPA.
    Type: Application
    Filed: December 6, 2022
    Publication date: January 30, 2025
    Inventors: Loren J. Swenson, Jed D. Whittaker, George E.G. Sterling
  • Publication number: 20250040454
    Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
    Type: Application
    Filed: July 31, 2024
    Publication date: January 30, 2025
    Inventors: Loren J. Swenson, George E.G. Sterling, Mark H. Volkmann, Colin C. Enderud
  • Patent number: 12206385
    Abstract: A superconducting circuit may include a transmission line having at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. The transmission line inductance may have a value selected to at least partially compensate for a variation in a characteristic impedance of the transmission line, the variation caused at least in part by the coupling capacitance. The coupling capacitance may be distributed along the length of the transmission line. A superconducting circuit may include a transmission line having at least one transmission line capacitance, a superconducting resonator, and a coupling inductance that communicatively couples the superconducting resonator to the transmission line. The transmission line capacitance may be selected to at least partially compensate for a variation in coupling strength between the superconducting resonator and the transmission line.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: January 21, 2025
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Jed D. Whittaker, Loren J. Swenson, Mark H. Volkmann
  • Patent number: 12204002
    Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: January 21, 2025
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, Emile M. Hoskinson, Mark H Volkmann, Andrew J. Berkley, George E. G. Sterling, Jed D. Whittaker
  • Publication number: 20250023518
    Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
    Type: Application
    Filed: June 4, 2024
    Publication date: January 16, 2025
    Inventors: Andrew J. BERKLEY, Loren J. SWENSON, Mark H. VOLKMANN, Jed D. WHITTAKER, Paul I. BUNYK, Peter D. SPEAR, Christopher B. RICH
  • Publication number: 20250013900
    Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
    Type: Application
    Filed: February 16, 2024
    Publication date: January 9, 2025
    Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T.E. Wilkinson, Trevor Michael Lanting
  • Patent number: 12102017
    Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 24, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, George E. G. Sterling, Mark H. Volkmann, Colin C. Enderud
  • Publication number: 20240237555
    Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material.
    Type: Application
    Filed: February 17, 2022
    Publication date: July 11, 2024
    Inventors: Colin C. Enderud, Mohammad H. Amin, Loren J. Swenson
  • Patent number: 12034404
    Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: July 9, 2024
    Assignee: 1372934 B.C. LTD.
    Inventors: Andrew J. Berkley, Loren J. Swenson, Mark H. Volkmann, Jed D. Whittaker, Paul I. Bunyk, Peter D. Spear, Christopher B. Rich
  • Publication number: 20240151782
    Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 9, 2024
    Inventors: Loren J. Swenson, Emile M. Hoskinson, Mark H. Volkmann, Andrew J. Berley, George E.G. Sterling, Jed D. Whittaker
  • Publication number: 20240138268
    Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material.
    Type: Application
    Filed: February 17, 2022
    Publication date: April 25, 2024
    Inventors: Colin C. Enderud, Mohammad H. Amin, Loren J. Swenson
  • Patent number: 11957065
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 9, 2024
    Assignee: 1372934 B.C. LTD.
    Inventors: Shuiyuan Huang, Byong H. Oh, Douglas P. Stadtler, Edward G. Sterpka, Paul I. Bunyk, Jed D. Whittaker, Fabio Altomare, Richard G. Harris, Colin C. Enderud, Loren J. Swenson, Nicolas C. Ladizinsky, Jason J. Yao, Eric G. Ladizinsky
  • Patent number: 11941486
    Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: March 26, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T. E. Wilkinson, Trevor Michael Lanting
  • Patent number: 11879950
    Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 23, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, Emile M. Hoskinson, Mark H. Volkmann, Andrew J. Berkley, George E. G. Sterling, Jed D. Whittaker
  • Patent number: 11874344
    Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: January 16, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, Andrew J. Berkley, Mark H. Volkmann, George E. G. Sterling, Jed D. Whittaker
  • Patent number: 11847534
    Abstract: A superconducting readout system employing a microwave transmission line, and a microwave superconducting resonator communicatively coupled to the microwave transmission line, and including a superconducting quantum interference device (SQUID), may be advantageously calibrated at least in part by measuring a resonant frequency of the microwave superconducting resonator in response to a flux bias applied to the SQUID, measuring a sensitivity of the resonant frequency in response to the flux bias, and selecting an operating frequency and a sensitivity of the microwave superconducting resonator based at least in part on a variation of the resonant frequency as a function of the flux bias. The flux bias may be applied to the SQUID by an interface inductively coupled to the SQUID. Calibration of the superconducting readout system may also include determining at least one of a propagation delay, a microwave transmission line delay, and a microwave transmission line phase offset.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 19, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Jed D. Whittaker, Loren J. Swenson, Ilya V. Perminov, Abraham J. Evert, Peter D. Spear, Mark H. Volkmann, Catia Baron Aznar, Michael S. Babcock