Patents by Inventor Loren Jones

Loren Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9148192
    Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: September 29, 2015
    Assignee: XILINX, INC.
    Inventors: Alan C. Wong, Christopher J. Borrelli, Loren Jones, Seu Wah Low, Parag Upadhyaya, Robert M. Ondris, Sarosh I. Azad
  • Patent number: 9003221
    Abstract: An embodiment for skew compensation for a stacked die is disclosed. For an embodiment of an apparatus, an interposer has a first and a second integrated circuit die coupled to the interposer. The first integrated circuit die includes an information generator, a signal delay compensator, and an input/output block. The information generator is configured to determine: a first delay value for a first path of the interposer between the first integrated circuit die and the second integrated circuit die; a second delay value for a second path of the interposer between the first integrated circuit die and the second integrated circuit die; and a difference between the first delay value and the second delay value. The signal delay compensator is coupled to receive the difference and configured to adjust a parameter of the first integrated circuit die to reduce the difference.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 7, 2015
    Assignee: Xilinx, Inc.
    Inventors: Khaldoon S. Abugharbieh, Daniel J. Ferris, III, Loren Jones, Austin H. Lesea
  • Patent number: 8386828
    Abstract: Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 26, 2013
    Assignee: Xilinx, Inc.
    Inventors: Sai Lalith Chaitanya Ambatipudi, Seu Wah Low, Christopher J. Borrelli, Loren Jones