Abstract: An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal is disclosed. The translator includes an output stage having an output node and a first output switching means for coupling the output node to a first voltage supply and a second output switching means for coupling the output node to a second voltage supply. A first input stage activates the first output switching means of the output stage in response to one of the differential ECL signals, and a second input stage activates the second output switching means of the output stage in response to the other differential ECL signal. The first input stage includes a first input switching means for coupling a first resistive element between the first voltage supply and the output node of the output stage, and the second input stage includes a second input switching means for coupling a second resistive element between the first voltage supply and the second voltage supply.

Abstract: An improved Emitter-Coupled Logic (ECL) circuit having a voltage comparator circuit connected to an emitter follower output circuit, the emitter follower output circuit includes an npn transistor having an emitter connected through a resistor to a voltage supply, and wherein the emitter follower output circuit produces a current in the resistor during operation of the ECL circuit, an improvement in the emitter follower output circuit including programmable connecting means for connecting the emitter follower output circuit to any one of a plurality of alternative voltage supplies, and maintaining means for maintaining substantially the same level of current in the resistor when the emitter follower output circuit is connected to any one of the plurality of alternative voltage supplies.

Abstract: An ECL/TTL translation circuit for translating ECL level input signals, which have a high voltage state and a low voltage state, to TTL level output signal, which have a high voltage state and a low voltage state. The translation circuit includes an ECL input circuit, a level shifter, and a TTL output circuit. The ECL input circuit receives the ECL level input signals and generates an intermediate voltage signal corresponding to the ECL level input signal. The level shifter is coupled to the ECL input circuit and maintains the intermediate voltage signal in a desired range of voltages. The TTL output circuit receives the intermediate voltage signal and generates a TTL output signal that corresponds to the intermediate voltage signal and, therefore, corresponds to the ECL input signal.

Abstract: A TTL/ECL translation circuit for translating TTL level input signals, which have a high voltage state and a low voltage state, to ECL level output signals, which have a high voltage state and a low voltage state. The translation circuit includes a TTL input circuit, a level shifter, and an ECL output circuit connected in series. The TTL input circuit receives the TTL level input signals and generates a first intermediate signal, corresponding to the TTL level input signals, that is transmitted to the level shifter. The level shifter receives the first intermediate signal and generates a second intermediate signal corresponding to the first intermediate signal that is transmitted to the ECL output circuit. The ECL output circuit receives the second intermediate signal and generates an ECL output signal corresponding to the second intermediate signal and the TTL input signal.

Abstract: An ECL/TTL translation circuit for translating ECL level input signals, which have a high voltage state and a low voltage state, to TTL level output signal, which have a high voltage state and a low voltage state. The translation circuit includes an ECL input circuit, a level shifter, a TTL output circuit a tristate controller. The ECL input circuit receives the ECL level input signals and generates an intermediate voltage signal corresponding to the ECL level input signal. The level shifter is coupled to the ECL input circuit and maintains the intermediate voltage signal in a desired range of voltages. The TTL output circuit receives the intermediate voltage signal and generates a TTL output signal that corresponds to the intermediate voltage signal and, therefore, corresponds to the ECL input signal. The tristate controller receives the tristate signal and causes the TTL output circuit to enter a high impedance mode when a high level tristate signal is received.