Abstract: All instruction words of a microprocessor have the same number of instruction word bits, but the number of instruction word bits constituting address bits varies as a function of the number of addresses associated with the operation specified by the operation code part of the instruction word. Operations having only one associated address have no address bits. A translator circuit has a plurality of inputs each receiving one bit of the instruction word, a set of control outputs for furnishing control signals, and a set of address outputs for furnishing address words. The set of control outputs has logic interconnections with each of the translator circuit inputs, as does the set of address outputs. Operation code bits in the instruction word are therefore also utilized as address bits, thereby decreasing the total number of instruction word bits required. For some operations, the required address is an operand stored in a memory location addressed by the operation code bits of the instruction word.

Abstract: A method and apparatus are provided for detecting the transition of digital data signals the two states of which are modulated with two different signal frequencies from one signal frequency to the other signal frequency. Timing elements generate comparison pulses having a first and second duration at each pulse front of the modulated data signal during a second and first signal frequency respectively. The comparison pulses in turn are used to generate control pulses so that the leading edge of the control pulse coincides with the leading edge of the comparison pulse, and likewise, the trailing edge of the control pulse coincides with the trailing edge of the comparison pulse. The control pulses are fed to the up/down counting direction control input of a reversible counter having a clock signal connected to its input. A pair of comparators compare the contents of the reversible counter with a pair of preset separate threshold levels.