Patents by Inventor Lorenzo Ciampolini

Lorenzo Ciampolini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12362011
    Abstract: A static random access memory device includes a memory matrix provided with at least one set of SRAM memory cells and a circuit for initializing cells of the set, the setting circuit being able to carry out various setting types and in particular a “deterministic” setting in which the cells are established at an imposed value and to carry out a “free” setting in which the cells are established at a value that depends on their manufacturing method.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: July 15, 2025
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Philippe Noel, Bastien Giraud, Lorenzo Ciampolini
  • Publication number: 20240203485
    Abstract: A static random access memory device comprising a memory array provided with SRAM memory cells, each of said cells in said array comprising a first storage node and a second storage node, the device further being provided with a control circuit for controlling said cells configured to, after powering up the array, place the array into a first operating mode in which a first set of cells located in a first zone of the array into a so-called “metastable” state for which the first storage node and said second storage node are placed to equal or substantially equal potentials while a second set of cells located in a second zone of the array distinct from the first zone have their respective first node and second node to respective different potentials and corresponding to a given logic state between a low state and a high state and to a logic state complementary to said given state.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 20, 2024
    Inventors: Jean-Philippe NOEL, Merlin GERBAUD, Bastien GIRAUD, Lorenzo CIAMPOLINI
  • Publication number: 20230127142
    Abstract: A static random access memory device includes a memory matrix provided with at least one set of SRAM memory cells and a circuit for initializing cells of the set, the setting circuit being able to carry out various setting types and in particular a “deterministic” setting in which the cells are established at an imposed value and to carry out a “free” setting in which the cells are established at a value that depends on their manufacturing method.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 27, 2023
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Philippe NOEL, Bastien GIRAUD, Lorenzo CIAMPOLINI
  • Patent number: 8995160
    Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 31, 2015
    Assignee: STMicroelectronics SA
    Inventors: Olivier Menut, David Turgis, Lorenzo Ciampolini
  • Publication number: 20140347907
    Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 27, 2014
    Applicant: STMicroelectronics S.A.
    Inventors: Olivier Menut, David Turgis, Lorenzo Ciampolini
  • Publication number: 20140347906
    Abstract: A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data item) and a second storage cell (storing a potential representing the second reference binary data item). A comparison circuit is connected to the first and second storage circuits and to the input terminal SL. A comparison node presents a potential representing the comparison of the input binary data item with the first and second reference data items. The comparison node is connected to an output stage, and the output stage is connected to the match line. The signal on the match line is based on the potential of the comparison node.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 27, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Olivier Menut, David Turgis, Lorenzo Ciampolini