Abstract: A silicon sensor device includes: a plurality of metal layers; and a plurality of dielectric layers. Each of the plurality of metal layers is disposed on a respective dielectric layer, and wherein each of the plurality of metal layers is separated from an adjacent metal layer by a respective dielectric layer. The plurality of metal layers include: a first metal layer comprising a plurality of transmitter electrodes and a plurality of receiver electrodes; a second metal layer disposed beneath the first metal layer, wherein the second metal layer comprises a plurality of routing traces for the plurality of transmitter electrodes and a plurality of shielding blocks; and one or more circuit layers disposed beneath the second metal layer. A respective shielding block of the plurality of shielding blocks is configured to shield a respective portion of a respective receiver electrode of the plurality of receiver electrodes.

Abstract: A silicon sensor device includes: a plurality of metal layers; and a plurality of dielectric layers. Each of the plurality of metal layers is disposed on a respective dielectric layer, and wherein each of the plurality of metal layers is separated from an adjacent metal layer by a respective dielectric layer. The plurality of metal layers include: a first metal layer comprising a plurality of transmitter electrodes and a plurality of receiver electrodes; a second metal layer disposed beneath the first metal layer, wherein the second metal layer comprises a plurality of routing traces for the plurality of transmitter electrodes and a plurality of shielding blocks; and one or more circuit layers disposed beneath the second metal layer. A respective shielding block of the plurality of shielding blocks is configured to shield a respective portion of a respective receiver electrode of the plurality of receiver electrodes.

Abstract: A circuit includes a controller circuit configured to receive an output voltage of a converter and adjust a switching frequency of the converter in response to a status of an output load and an output load sensing circuit configured to determine the status of the output load and provide the peak current to the controller circuit. The output load sensing circuit may include a first timer configured to provide a delayed first signal to a peak current control in response to the output load being a heavy load. A second timer may be configured to provide a delayed second signal to the peak current control in response to the output load being a light load. The peak current control may be configured to adjust a peak current based on the received first signal and the second signal and configured to provide the peak current to the controller circuit.

Abstract: Disclosed herein are systems and methods for improved performance of phase-locked loop based clock generators, particularly in the context of wireless audio. A PLL clock generator includes a PLL core configured to receive a module reference clock provided by a communications module and generate a subsystem data clock corresponding to a module data clock of the communications module; and a data clock tracker module configured to receive the module data and subsystem data clocks and determine a corresponding data clock correction factor. The bandwidth of the PLL core may be dynamically changed thereby enabling both fast and very precise settling. The PLL core may use a low jitter frequency reference for the phase detector while an a synchronous and jitter-prone audio sample clock is used to ensure a mean frequency of the PLL core tracks the audio sample clock.

Abstract: Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

Abstract: Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

Abstract: Systems and methods include a digital control module that receives and processes audio data for output through a loudspeaker. An analog block receives the audio data and the power control signal and amplifies the audio data for output. A first processing path includes a buffer to delay the audio data, a first component to combine the buffered audio data and anti-noise. A second processing path includes an absolute value block to receive the audio data and an envelope detector to receive the absolute value data and generate a maximum value for the envelope. An anti-noise path includes an absolute value block configured to determine an anti-noise absolute value which is combined with the absolute value anti-noise data. A power generator receives the output from the envelope detector and updates a power level to approximate a minimum powered needed to process the audio signal.

Abstract: Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

Abstract: Disclosed herein are systems and methods for improved performance of phase-locked loop based clock generators, particularly in the context of wireless audio. A PLL clock generator includes a PLL core configured to receive a module reference clock provided by a communications module and generate a subsystem data clock corresponding to a module data clock of the communications module; and a data clock tracker module configured to receive the module data and subsystem data clocks and determine a corresponding data clock correction factor. The bandwidth of the PLL core may be dynamically changed thereby enabling both fast and very precise settling. The PLL core may use a low jitter frequency reference for the phase detector while an a synchronous and jitter-prone audio sample clock is used to ensure a mean frequency of the PLL core tracks the audio sample clock.

Abstract: A circuit includes a controller circuit configured to receive an output voltage of a converter and adjust a switching frequency of the converter in response to a status of an output load and an output load sensing circuit configured to determine the status of the output load and provide the peak current to the controller circuit. The output load sensing circuit may include a first timer configured to provide a delayed first signal to a peak current control in response to the output load being a heavy load. A second timer may be configured to provide a delayed second signal to the peak current control in response to the output load being a light load. The peak current control may be configured to adjust a peak current based on the received first signal and the second signal and configured to provide the peak current to the controller circuit.

Abstract: Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.

Abstract: Systems and methods are provided for improved stability of driver amplifiers. In one example, a system includes an NMOSFET power device operable to generate a current signal at a drain terminal. The system further includes a current comparison amplifier operable to amplify a difference signal comprising a difference between a replica current signal of the NMOSFET power device and a reference current signal to drive a current comparison amplifier voltage output signal. The system further includes a PMOSFET clamp device comprising a source terminal coupled to a gate terminal of the NMOSFET power device operable to limit a voltage at the gate terminal of the NMOSFET power device responsive to the current comparison amplifier voltage output signal.

Abstract: A voice-activity detector (VAD) system comprises a microphone operable to receive and to process audio inputs from an environment to generate an analog audio input signal. The system further comprises an analog VAD operable to process the analog audio input signal to perform an initial detection of human speech, and operable to send a wake up command to a digital signal processing chain to awaken the digital signal processing chain from a sleep mode, when the analog VAD detects human speech. Further, the system comprises the digital signal processing chain operable to process the analog audio input signal to perform a secondary detection of human speech, and operable to output a signal indicating that human speech is detected, when the digital signal processing chain detects human speech. In one or more embodiments, the secondary detection of human speech is more accurate than the initial detection of human speech.

Abstract: Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

Abstract: Systems and methods according to one or more embodiments are provided for sensing a current at an output of a switching amplifier. In one example, a system includes a first transistor switch coupled to a load configured to conduct a current in the load responsive to a first pulse width modulated control signal coupled to a gate terminal of the first transistor switch. The system further includes a second transistor switch configured to conduct the current in the load responsive to a second pulse width modulated control signal coupled to a gate terminal of the second transistor switch. A shielding switch is coupled between the load and a current sensing circuit, wherein the shielding switch is configured to provide a small signal voltage to the current sensing circuit in response to the second pulse width modulated control signal, the current sensing circuit is configured to sense the current traveling through the load responsive to the small signal voltage.

Abstract: Systems and methods include a digital control module that receives and processes audio data for output through a loudspeaker. An analog block receives the audio data and the power control signal and amplifies the audio data for output. A first processing path includes a buffer to delay the audio data, a first component to combine the buffered audio data and anti-noise. A second processing path includes an absolute value block to receive the audio data and an envelope detector to receive the absolute value data and generate a maximum value for the envelope. An anti-noise path includes an absolute value block configured to determine an anti-noise absolute value which is combined with the absolute value anti-noise data. A power generator receives the output from the envelope detector and updates a power level to approximate a minimum powered needed to process the audio signal.

Abstract: Systems and methods are provided for improved noise performance of audio amplifiers. In one example, a system includes a multistage amplifier comprising at least a first stage amplifier and a second stage amplifier. The system further includes a plurality of switches disposed within the multistage amplifier to configure the multistage amplifier. The system further includes a control signal configured to control the multistage amplifier to a normal amplification mode or a mute state, wherein the multistage amplifier is adapted to amplify an input signal in the normal amplification mode, the multistage amplifier is adapted to output a zero signal in the mute state, and internal amplification stages of the multistage amplifier are disabled in the mute state, and output stages of each of the at least first stage amplifier and the second stage amplifier are electrically shorted and/or shorted to a fixed bias voltage in the mute state.

Abstract: Systems and methods according to one or more embodiments provide a low power current steering digital-to-analog converter. In one example, a device includes a current cell including a plurality of switches. The device further includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state before the current cell receives the first data signal. Related systems and methods are also provided.

Abstract: Systems and methods according to one or more embodiments provide a low power current steering digital-to-analog converter. In one example, a device includes a current cell including a plurality of switches. The device further includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state before the current cell receives the first data signal. Related systems and methods are also provided.

Abstract: Systems and methods are provided for improved noise performance of audio amplifiers. In one example, a system includes a multistage amplifier comprising at least a first stage amplifier and a second stage amplifier. The system further includes a plurality of switches disposed within the multistage amplifier to configure the multistage amplifier. The system further includes a control signal configured to control the multistage amplifier to a normal amplification mode or a mute state, wherein the multistage amplifier is adapted to amplify an input signal in the normal amplification mode, the multistage amplifier is adapted to output a zero signal in the mute state, and internal amplification stages of the multistage amplifier are disabled in the mute state, and output stages of each of the at least first stage amplifier and the second stage amplifier are electrically shorted and/or shorted to a fixed bias voltage in the mute state.