Patents by Inventor Loreto Cantillep

Loreto Cantillep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked die assembly having reduced stress electrical interconnects
    Patent number: 8912661
    Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: December 16, 2014
    Assignee: Invensas Corporation
    Inventors: Scott McGrath, Jeffrey S. Leal, Ravi Shenoy, Loreto Cantillep, Simon McElrea, Suzette K. Pangrle
  • Electrically interconnected stacked die assemblies
    Patent number: 8723332
    Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: May 13, 2014
    Assignee: Invensas Corporation
    Inventors: Simon J. S. McElrea, Lawrence Douglas Andrews, Jr., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
  • Electrically interconnected stacked die assemblies
    Patent number: 8629543
    Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 14, 2014
    Assignee: Invensas Corporation
    Inventors: Simon J. S. McElrea, Lawrence Douglas Andrews, Jr., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
  • STACKED DIE ASSEMBLY HAVING REDUCED STRESS ELECTRICAL INTERCONNECTS
    Publication number: 20110272825
    Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.
    Type: Application
    Filed: November 4, 2010
    Publication date: November 10, 2011
    Applicant: Vertical Circuits, Inc.
    Inventors: Scott McGrath, Jeffrey S. Leal, Ravi Shenoy, Loreto Cantillep, Simon J. S. McElrea, Suzette K. Pangrle
  • Electrically Interconnected Stacked Die Assemblies
    Publication number: 20110037159
    Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 17, 2011
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J. S. McElrea, Lawrence Douglas Andrews, JR., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
  • ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES
    Publication number: 20080303131
    Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
    Type: Application
    Filed: May 20, 2008
    Publication date: December 11, 2008
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J.S. McElrea, Lawrence Douglas Andrews, JR., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep