Patents by Inventor Loreto Y. Cantillep

Loreto Y. Cantillep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6750534
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: June 15, 2004
    Assignee: ST Assembly Test Services Ltd
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee
  • Patent number: 6432742
    Abstract: A method of fabricating a die-up laminated PBGA package, including the following steps. A mold chase for a PBGA package is provided. The mold chase has an open side with and exposed bottom wall and side walls, and a bottom side. The mold chase is positioned open side up. A heat spreader is dropped into the mold chase open side. The heat spreader has a lower protruding section, and lateral peripheral flanges with gaps therebetween. The protruding section contacts a portion of the bottom wall of the mold chase and the flanges contact a portion of the exposed side walls of the mold chase to thereby secure the heat spreader within the mold chase. A substrate, having a die affixed thereto in a die down position, is fixedly placed over the mold chase. The die being positioned within the space above the protruding section of the heat spreader.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: August 13, 2002
    Assignee: St Assembly Test Services Pte Ltd.
    Inventors: Chow Seng Guan, John Briar, Loreto Y. Cantillep
  • Publication number: 20020093095
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 18, 2002
    Applicant: ST ASSEMBLY TEST SERVICES PTE LTD
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee
  • Patent number: 6403401
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: June 11, 2002
    Assignee: St Assembly Test Services Pte Ltd
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee