Abstract: A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Abstract: A process for producing a plurality of metallized vias in a polyimide dielectric is disclosed. The process includes depositing a polyimide precursor, then a silane and finally a metal, after patterning the polyimide and silane. The sandwich is heated to completely imidize the polyimide, crosslink the silane and anneal the metal simultaneously. The excess metal overlying the polyimide between the vias is removed by chemical mechanical polishing using the crosslinked silane as a polish stop.

Abstract: A process for producing a plurality of metallized vias in a polyimide dielectric is disclosed. The process includes depositing a polyimide precursor, then a silane and finally a metal, after patterning the polyimide and silane. The sandwich is heated to completely imidize the polyimide, crosslink the silane and anneal the metal simultaneously. The excess metal overlying the polyimide between the vias is removed by chemical mechanical polishing using the crosslinked silane as a polish stop.