Patents by Inventor Lori A. Dicks
Lori A. Dicks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5161729Abstract: Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at lest one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.Type: GrantFiled: July 11, 1991Date of Patent: November 10, 1992Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks, Jerald M. Loy
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Patent number: 5101550Abstract: A method and apparatus for accurately positioning a semiconductor chip onto a die bond pad region of a semiconductor package. A frame is constructed for slidable contact with peripheral walls of a semiconductor package die cavity. A frame central aperture with a wide upper opening and a narrower lower opening guides a semiconductor chip dropped therethrough into a precise position in the die cavity.Type: GrantFiled: July 25, 1991Date of Patent: April 7, 1992Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks
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Patent number: 5099306Abstract: Disclosed is a stacked leadframe assembly for use with integrated circuit chips. The assembly comprises multiple leadframes arranged in stacked relation. Each leadframe comprises conductive elements and solder bumps for electrically and mechanically connecting selected conductive elements of the leadframes.Type: GrantFiled: March 26, 1991Date of Patent: March 24, 1992Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Jerald M. Loy, Lori A. Dicks, Francis J. Belcourt
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Patent number: 5074036Abstract: A method and apparatus for accurately positioning a semiconductor chip onto a die bond pad region of a semiconductor package. A frame is constructed for slidable contact with peripheral walls of a semiconductor package die cavity. A frame central aperture with a wide upper opening and a narrower lower opening guides a semiconductor chip dropped therethrough into a precise position in the die cavity.Type: GrantFiled: October 31, 1990Date of Patent: December 24, 1991Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks
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Patent number: 5066614Abstract: Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at least one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.Type: GrantFiled: September 28, 1990Date of Patent: November 19, 1991Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks, Jerald M. Loy
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Patent number: 5010387Abstract: Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at least one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.Type: GrantFiled: November 21, 1988Date of Patent: April 23, 1991Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks, Jerald M. Loy
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Patent number: 4979289Abstract: A method and apparatus for accurately positioning a semiconductor chip onto a die bond pad region of a semiconductor package. A removable non-wettable by solder frame is constructed for slidable contact with peripheral walls of a semiconductor package die cavity. A frame central aperture with a wide upper opening and a narrower lower opening guides a semiconductor chip dropped therethrough into a precise position in the die cavity.Type: GrantFiled: February 10, 1989Date of Patent: December 25, 1990Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks
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Patent number: 4980753Abstract: Disclosed is a low-cost high-performance semiconductor chip package enabling a direct chip to printed circuit board connection. The package comprises a semiconductor chip having a front surface and a back surface. The front surface comprises pads for input and output of signals to and from the chip. The package further comprises a leadframe having power, ground, and signal conductive elements having first and second end portions for transmitting input and output signals to the pads. The package also comprises a bonding system for selectively connecting the first end portions of the conductive elements to the pads and a protective system for providing sealed and environmental protection around the semiconductor chip and portions of the leadframe while permitting other portions of the leadframe to protrude from the protective means to provide connection with other devices.Type: GrantFiled: November 21, 1988Date of Patent: December 25, 1990Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks
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Patent number: 4948032Abstract: Disclosed in a fluxing agent comprising 45% to 55% by weight of peanut oil and 45% to 55% by weight of water-white rosin.Type: GrantFiled: November 21, 1988Date of Patent: August 14, 1990Assignee: Atmel CorporationInventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks
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Patent number: 4898320Abstract: Disclosed is a method of manufacturing a high-yield solder bumped semiconductor wafer. The method comprises providing a non-solderable transfer substrate having a transfer surface for receipt of solder material; depositing solder material onto the transfer surface to form solder bumps in a predetermined pattern; aligning solderable conductive elements of a semiconductor wafer with the predetermined solder bumps on the transfer surface; and reflowing the patterned solder bumps into wetted contact with the wafer conductive elements.Type: GrantFiled: November 21, 1988Date of Patent: February 6, 1990Assignee: Honeywell, Inc.Inventors: Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks
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Patent number: 4892245Abstract: Disclosed is a system and method for controlled compression furnace bonding of a semiconductor chip to conductive elements of a leadframe. The system comprises a holding member having a chip support surface for supporting a semiconductor chip and a positioning system for precisely positioning conductive elements of a leadframe with corresponding bonding locations on the semiconductor chip. A furnace heating system comprising a furnace is employed for heating and bonding the conductive elements to the chip bonding locations.Type: GrantFiled: November 21, 1988Date of Patent: January 9, 1990Assignee: Honeywell Inc.Inventors: Thomas J. Dunaway, Richard K. Speilberger, Jerald M. Loy, Lori A. Dicks, Luverne O. Balgaard