Abstract: A process chamber including: a chamber body enclosing an interior volume; a substrate support disposed in the interior volume that includes a lower interior volume below the substrate support and an upper interior volume above the substrate support; a first purge gas line configured to provide a first flow of purge gas to the lower interior volume; and a gas flow ring disposed around an outer edge of the substrate support, the gas flow ring comprising: a ring-shaped body; a top surface; a bottom surface; a first overlapping portion extending from a first inner sidewall of the ring-shaped body; and a second overlapping portion extending from a second inner sidewall of the ring-shaped body. The first overlapping portion is spaced apart from and overlies the second overlapping portion to form a gas flow channel that extends from the bottom surface to the top surface of the gas flow ring.

Abstract: The present disclosure relates to a radiation reflector assembly for use with a semiconductor processing chamber and a substrate processing system having the radiation reflector assembly. The radiation reflector assembly includes a shell body that includes an interior cylindrical wall; and a reflector disk that includes a center hole, a bottom reflective surface, and a top surface. The reflector disk is disposed within and spaced from the interior cylindrical wall in a manner that permits fluid to flow therebetween. The radiation reflector assembly includes an actuator coupled to the reflector disk, and the actuator is operable to axially displace the reflector disk relative to the shell body. The radiation reflector assembly includes an elongated tube extending through the center hole of the reflector disk. A method of processing a substrate with the radiation reflector assembly is also described.

Abstract: A method and apparatus for a process chamber for thermal processing is described herein. The process chamber is a dual process chamber and shares a chamber body. The chamber body includes a first and a second set of gas inject passages. The chamber body may also include a first and a second set of exhaust ports. The process chamber may have a shared gas panel and/or a shared exhaust conduit.

Abstract: A susceptor for processing a substrate is provided including a base and a coating formed over the base. The base includes an outer rim having an inner edge, an outer edge, and a top connecting the inner edge to the outer edge; and an inner dish disposed inside the outer rim and coupled to the outer rim, the inner dish recessed from the top of the outer rim, the inner dish having a front side and an opposing back side. The coating has an outer surface that includes a first portion formed over the front side of the inner dish. The first portion of the outer surface of the coating includes a first region and a second region, the first region has a first average level of roughness, the second region has a second average level of roughness.

Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In an embodiment, an adjustable reflector includes a plurality of reflector elements. Each of the plurality of elements as a first surface, a second surface, and a plurality of sidewalls. The first surface is a reflective surface and is configured to face a lamp. The adjustable reflector includes one or more actuation mechanisms coupled to the plurality of elements. A method of thermally processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under or over a lamp and the adjustable reflector, and in response to the thermal intensity being outside of desired parameters, adjusting the reflector profile of the reflector assembly along a centerline path.

Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In an embodiment, an adjustable reflector assembly includes a plurality of elements including at least one stationary element and at least one rotating element, wherein a first surface of each of the plurality of elements is a reflective surface, and at least one actuation mechanism configured to actuate the at least one rotating element relative to the stationary element. A method of processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under a lamp and the reflector assembly, determining if the thermal intensity is outside of desired parameters, and in response to the thermal intensity being outside of desired parameters, and adjusting a reflector profile of the reflector assembly.

Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In one embodiment, a substrate processing chamber includes a lid, a floor, and a processing volume between the lid and the floor. An upper window is disposed between the lid and the processing volume, a lower window is disposed between the floor and the processing volume. A lamp head is disposed between the lower window and the floor or between the upper window and the lid. At least one lamp is disposed within the lamp head, and a lens is disposed between the lamp head and the processing volume. In another embodiment, a plurality of lamps is disposed within the lamp head including at least one first lamp operating at a first wavelength and at least one second lamp operating at a second wavelength.

Abstract: In one embodiment, a processing chamber, suitable for use in semiconductor processing, includes a chamber body enclosing an interior volume. A susceptor is disposed in the interior volume, and the interior volume includes a purge interior volume below the susceptor and a process volume above the substrate support. A liner is disposed radially outward of the susceptor. The processing chamber also includes a preheat ring. The preheat ring is configured to engage the susceptor when the susceptor is an elevated processing position and to engage the liner when the susceptor is in a lowered loading/unloading position.

Abstract: Embodiments herein provide for a method of processing a semiconductor substrate. The method described herein may include receiving a first input corresponding to a first geometric hardware configuration of a process chamber, receiving a second input corresponding to a first process recipe of the process chamber, determining, based on the first input and the second input, a first purge gas flow rate for the process chamber, measuring a deposition characteristic of the process chamber via a first sensor, determining, based on the first input, the second input, and the measured deposition characteristic, a second purge gas flow rate, the second purge gas flow rate different from the first purge gas flow rate, and flowing a purge gas at the second purge gas flow rate during a deposition process.

Abstract: Systems and apparatus for a reduced mass substrate support are disclosed, according to certain embodiments. A front side pocket is provided for support of a substrate, while a backside pocket is provided that reduces the mass of the substrate support. By providing the backside pocket, the mass of the overall substrate support is reduced, providing faster thermal cycling times for the substrate support and reducing the weight of the substrate support for transport. Lift pin systems, according to disclosed embodiments, are compatible with existing pedestal systems by providing a hollow extension from each lift pin hole that extends from a bottom of the backside pocket to provide support for lift pin insertion and operation.

Abstract: Aspects of the disclosure relate to processes for epitaxial growth of Group III/V materials at high rates, such as about 30 ?m/hr or greater, for example, about 40 ?m/hr, about 50 ?m/hr, about 55 ?m/hr, about 60 ?m/hr, about 70 ?m/hr, about 80 ?m/hr, and about 90-120 ?m/hr deposition rates. The Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. The Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers containing gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

Abstract: A growth structure having a lattice transition under a release layer is used as a seed crystal for growth of optoelectronic devices. The optoelectronic device can be a single- or multi-junction photovoltaic device. The release layer can be selectively removed in an epitaxial lift-off (ELO) process to separate the optoelectronic device from the growth structure and leave the region with the lattice transition intact to reuse the growth structure to grow additional devices. A manufacturing method is described that includes providing a growth structure having a substrate and a lattice transition from a first lattice constant to a second lattice constant, depositing a release layer on the growth structure, depositing on the release layer an epitaxial layer having a lattice constant that matches the second lattice and including an optoelectronic device, and removing the release layer to separate the epitaxial layer and the optoelectronic device from the growth structure.

Abstract: An example method for chemical vapor deposition (CVD) of thin films includes providing a deposition zone in a reaction chamber having a fixed showerhead assembly that introduces CVD reactive gases under positive pressure into the deposition zone. The example method also includes moving a substrate carrier beneath the showerhead assembly in the reaction chamber, the substrate carrier supports and transports at least one substrate within the reaction chamber so as to be subjected to a CVD process by the CVD reactive gases. The example method also includes providing a liner assembly shrouding the deposition zone and including at least one partial enclosure around the deposition zone isolating the deposition zone and the substrate carrier, whereby solid reaction byproducts are plated onto material in the liner assembly and gaseous reaction byproducts flow radially outward, the liner assembly being mounted on the substrate carrier for motion with the substrate carrier.

Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

Abstract: A growth structure having a lattice transition under a release layer is used as a seed crystal for growth of optoelectronic devices. The optoelectronic device can be a single- or multi-junction photovoltaic device. The release layer can be selectively removed in an epitaxial lift-off (ELO) process to separate the optoelectronic device from the growth structure and leave the region with the lattice transition intact to reuse the growth structure to grow additional devices. A manufacturing method is described that includes providing a growth structure having a substrate and a lattice transition from a first lattice constant to a second lattice constant, depositing a release layer on the growth structure, depositing on the release layer an epitaxial layer having a lattice constant that matches the second lattice and including an optoelectronic device, and removing the release layer to separate the epitaxial layer and the optoelectronic device from the growth structure.

Abstract: A chemical vapor deposition (CVD) reactor comprises a deposition zone, a substrate carrier and a liner assembly. The deposition zone is constructed so as to have a positive pressure reactant gases fixed showerhead introducing reactant gas supporting thin film CVD deposition. The substrate carrier movably supports a substrate and the liner assembly within the deposition zone and is heated so as to be subjected to a CVD process. The liner assembly partly encloses selected portions of the deposition zone, particularly portions of the substrate carrier and thereby enclose a hot zone surrounding a substrate to be processed so as to retain heat in that zone but allows gas flow radially outwardly toward walls of a surrounding cold-wall reactor with exhaust ports surrounding the deposition zone that exhaust spent reactant gases. The liner assembly is a sink for solid reaction byproducts while gaseous reaction byproducts are pumped out at the exhaust ports.

Abstract: A showerhead for a semiconductor processing reactor formed by an array of showerhead tiles. Each showerhead tile has a plurality of process gas apertures, which may be in a central area of the tile or may extend over the entire tile. Each showerhead tile can be dimensioned for processing a respective substrate or a plurality of substrates or the array can be dimensioned for processing a substrate. An exhaust region surrounds the process gas apertures. The exhaust region has at least one exhaust aperture, and may include an exhaust slot, a plurality of connected exhaust slots or a plurality of exhaust apertures. The exhaust region surrounds the array of showerhead tiles, or a respective portion of the exhaust region surrounds the plurality of process gas apertures in each showerhead tile or group of showerhead tiles. A gas curtain aperture may be between the exhaust region and the process gas apertures of one of the showerhead tiles or adjacent to the central area of the tile.