Abstract: Methods are provided of fabricating a nitride semiconductor structure. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over one side of the substrate with a thermal chemical-vapor-deposition process. A second layer is similarly deposited over an opposite side of the substrate using the group-III precursor and the nitrogen precursor. The substrate is cooled after depositing the first and second layers without substantially deforming a shape of the substrate.

Abstract: Methods are provided of fabricating compound nitride semiconductor structures. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over a surface of a first substrate with a thermal chemical-vapor-deposition process. A second layer is deposited over a surface of a second substrate with the thermal chemical-vapor-deposition process using the first group-III precursor and the first nitrogen precursor. The first and second substrates are different outer substrates of a plurality of stacked substrates disposed within the processing chamber as a stack so that the first and second layers are deposited on opposite sides of the stack. Deposition of the first layer and deposition of the second layer are performed simultaneously.

Abstract: Apparatus and methods are described for fabricating a compound nitride semiconductor structure. Group-III and nitrogen precursors are flowed into a first processing chamber to deposit a first layer over a substrate with a thermal chemical-vapor-deposition process. The substrate is transferred from the first processing chamber to a second processing chamber. Group-III and nitrogen precursors are flowed into the second processing chamber to deposit a second layer over the first layer with a thermal chemical-vapor-deposition process. The first and second group-III precursors have different group-III elements.

Abstract: Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

Abstract: Provided herein is a wafer carrier comprising a disk and a pocket, wherein the pocket is centered in the disk and holds a wafer. Also provided is a method of processing or testing a wafer for a semiconductor device, comprising the steps of placing the wafer in the wafer carrier disclosed herein; loading the wafer carrier in a loadlock chamber; and transferring the wafer carrier from the loadlock chamber to a process chamber for processing or testing.