Patents by Inventor Lorraine Byrne

Lorraine Byrne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180275082
    Abstract: A structure for a chemical sensing device includes a plurality of recesses and a plurality of electrically conductive elements located in, and protruding from, the plurality of recesses.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
  • Patent number: 10078065
    Abstract: A structure for a chemical sensing device includes a plurality of recesses and a plurality of electrically conductive elements located in, and protruding from, the plurality of recesses.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: September 18, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
  • Patent number: 9780028
    Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer away from a raised feature. An interconnect is in contact with the raised feature through the reflow via.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: October 3, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
  • Publication number: 20170191176
    Abstract: Controlling dimensions of nanowires includes lithographically forming a trench in a layer of a polymer resin with a width less than one micrometer where the polymer resin has a thickness less than one micrometer and is deposited over an electrically conductive substrate, depositing a nanowire material within the trench to form a nanowire, and obtaining the nanowire from the trench with a removal mechanism.
    Type: Application
    Filed: March 15, 2017
    Publication date: July 6, 2017
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Graeme Scott, Kevin Dooley, Lorraine Byrne, Pat J. Reilly
  • Publication number: 20170146475
    Abstract: A structure for a chemical sensing device includes a plurality of recesses and a plurality of electrically conductive elements located in, and protruding from, the plurality of recesses.
    Type: Application
    Filed: July 25, 2016
    Publication date: May 25, 2017
    Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
  • Patent number: 9631291
    Abstract: Controlling dimensions of nanowires includes lithographically forming a trench in a layer of a polymer resin with a width less than one micrometer where the polymer resin has a thickness less than one micrometer and is deposited over an electrically conductive substrate, depositing a nanowire material within the trench to form a nanowire, and obtaining the nanowire from the trench with a removal mechanism.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: April 25, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Graeme Scott, Kevin Dooley, Lorraine Byrne, Pat J. Reilly
  • Publication number: 20170084533
    Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer away from a raised feature. An interconnect is in contact with the raised feature through the reflow via.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 23, 2017
    Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
  • Patent number: 9583432
    Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 28, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
  • Patent number: 9410911
    Abstract: A structure for a chemical sensing device, the structure comprising at least one electrically conductive element located in, and protruding from, at least one recess. A method of manufacturing the structure includes: (a) providing a template comprising at least one recess having a recess depth; (b) providing an electrically conductive material in the at least one recess; and (c) removing part of the template to decrease the recess depth of the at least one recess, thereby forming said protruding at least one electrically conductive element.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: August 9, 2016
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
  • Publication number: 20160104675
    Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.
    Type: Application
    Filed: January 29, 2013
    Publication date: April 14, 2016
    Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
  • Patent number: 8575025
    Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 5, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Fitzpatrick, Kevin Dooley, Lorraine Byrne
  • Publication number: 20130195140
    Abstract: The present invention relates to a temperature sensor comprising a network of carbon nanotubes, wherein an electrical resistance of the network of carbon nanotubes is indicative of a temperature to which the network of carbon nanotubes has been exposed. The present invention further relates to a time temperature indicator and a method of manufacturing a temperature sensor.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Inventors: Vittorio Scardaci, Graeme Scott, Richard Coull, Lorraine Byrne, Jonathan Coleman
  • Publication number: 20130187670
    Abstract: Apparatus and methods related to capacitive sensors are provided. Metal walls are formed in an interdigitated pattern. A dielectric material corresponding to a selected analyte is deposited in contact with the metal walls thus defining a capacitive sensor. Exposure to the analyte causes the electrical capacitance to vary in accordance with intensity. Analyte detection or measurement, data acquisition, or other operations can be performed by way of the capacitive sensors of the present teachings.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Inventors: Kevin Dooley, Lorraine Byrne, Graeme Scott, Vladek Kasperchik
  • Patent number: 8393077
    Abstract: A method for fabrication of passive electronic components includes disposing a sacrificial layer on a carrier and forming a curable resin layer on top of the sacrificial layer and patterning the curable resin to form a cured resin template having multiple pattern levels. A metal material is deposited into the first pattern level to form a first structure. A dielectric material is then formed on exposed portions of the first structure. A nonselective subtractive process is used to expose the sacrificial layer in a bottom of the second pattern level and metal material is deposited into the second pattern level and built up to include a portion which crosses over the dielectric material.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: March 12, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lorraine Byrne, Kevin Dooley, David Fitzpatrick
  • Publication number: 20130029481
    Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Inventors: David Fitzpatrick, Kevin Dooley, Lorraine Byrne
  • Publication number: 20120219702
    Abstract: A film can be patterned with a nanomaterial. Such patterning can, in various embodiments, be performed by applying a uniform mixture of a solute in a solvent to a surface of the film to form a coating of a soluble material on the surface of the film in a pre-defined pattern that defines coated parts of the film and uncoated parts of the film, depositing an aqueous dispersion, including the nanomaterial and a surfactant, on the defined coated and uncoated parts of the film, washing the film to remove the coating of the soluble material and the nanomaterial from the defined coated parts of the film, but not removing the nanomaterial from the defined uncoated parts of the film, along with removing the surfactant from the defined coated and uncoated parts of the film, and leaving a pattern of the nanomaterial on the defined uncoated parts of the film.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 30, 2012
    Inventors: Graeme Scott, Lorraine Byrne, Richard Coull, Vittorio Scardaci
  • Publication number: 20110063776
    Abstract: A method for fabrication of passive electronic components includes disposing a sacrificial layer on a carrier and forming a curable resin layer on top of the sacrificial layer and patterning the curable resin to form a cured resin template having multiple pattern levels. A metal material is deposited into the first pattern level to form a first structure. A dielectric material is then formed on exposed portions of the first structure. A nonselective subtractive process is used to expose the sacrificial layer in a bottom of the second pattern level and metal material is deposited into the second pattern level and built up to include a portion which crosses over the dielectric material.
    Type: Application
    Filed: September 15, 2009
    Publication date: March 17, 2011
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Lorraine Byrne, Kevin Dooley, David Fitzpatrick
  • Patent number: 7737006
    Abstract: A method of manufacturing an electronic component comprising at least one n- or p-doped portion, comprising the steps of: co-depositing inorganic semi-conducting nanoparticles and dopant on a substrate, the nanoparticles being a group four element such as silicon or germanium; fusing the nanoparticles by heating to form a continuous layer; and subsequently; and, recrystallising the layer.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: June 15, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul Colfer, Lorraine Byrne, Eugene Cahill, Phil Keenan, Niall Stobie
  • Publication number: 20060237719
    Abstract: A method of manufacturing an electronic component comprising at least one n- or p-doped portion, comprising the steps of: co-depositing inorganic semi-conducting nanoparticles and dopant on a substrate, the nanoparticles being a group four element such as silicon or germanium; fusing the nanoparticles by heating to form a continuous layer; and subsequently; and, recrystallising the layer.
    Type: Application
    Filed: October 30, 2003
    Publication date: October 26, 2006
    Inventors: Paul Colfer, Lorraine Byrne, Eugene Cahill, Phil Keenan, Niall Stobie
  • Publication number: 20060214577
    Abstract: A layer of a material is deposited onto a substrate of an electroluminescent lamp in accordance with a desired image. An action is performed to the material to render the material at least partially tacky. Electroluminescent powder is deposited onto the substrate. The electroluminescent powder adheres to the substrate where the material has been deposited thereon.
    Type: Application
    Filed: March 26, 2005
    Publication date: September 28, 2006
    Inventors: Lorraine Byrne, Philip Keenan, Anna Fenelon