Patents by Inventor Lorraine Byrne
Lorraine Byrne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180275082Abstract: A structure for a chemical sensing device includes a plurality of recesses and a plurality of electrically conductive elements located in, and protruding from, the plurality of recesses.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
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Patent number: 10078065Abstract: A structure for a chemical sensing device includes a plurality of recesses and a plurality of electrically conductive elements located in, and protruding from, the plurality of recesses.Type: GrantFiled: July 25, 2016Date of Patent: September 18, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
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Patent number: 9780028Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer away from a raised feature. An interconnect is in contact with the raised feature through the reflow via.Type: GrantFiled: November 29, 2016Date of Patent: October 3, 2017Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
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Publication number: 20170191176Abstract: Controlling dimensions of nanowires includes lithographically forming a trench in a layer of a polymer resin with a width less than one micrometer where the polymer resin has a thickness less than one micrometer and is deposited over an electrically conductive substrate, depositing a nanowire material within the trench to form a nanowire, and obtaining the nanowire from the trench with a removal mechanism.Type: ApplicationFiled: March 15, 2017Publication date: July 6, 2017Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Graeme Scott, Kevin Dooley, Lorraine Byrne, Pat J. Reilly
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Publication number: 20170146475Abstract: A structure for a chemical sensing device includes a plurality of recesses and a plurality of electrically conductive elements located in, and protruding from, the plurality of recesses.Type: ApplicationFiled: July 25, 2016Publication date: May 25, 2017Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
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Patent number: 9631291Abstract: Controlling dimensions of nanowires includes lithographically forming a trench in a layer of a polymer resin with a width less than one micrometer where the polymer resin has a thickness less than one micrometer and is deposited over an electrically conductive substrate, depositing a nanowire material within the trench to form a nanowire, and obtaining the nanowire from the trench with a removal mechanism.Type: GrantFiled: January 29, 2013Date of Patent: April 25, 2017Assignee: Hewlett-Packard Development Company, L.P.Inventors: Graeme Scott, Kevin Dooley, Lorraine Byrne, Pat J. Reilly
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Publication number: 20170084533Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer away from a raised feature. An interconnect is in contact with the raised feature through the reflow via.Type: ApplicationFiled: November 29, 2016Publication date: March 23, 2017Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
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Patent number: 9583432Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.Type: GrantFiled: January 29, 2013Date of Patent: February 28, 2017Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
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Patent number: 9410911Abstract: A structure for a chemical sensing device, the structure comprising at least one electrically conductive element located in, and protruding from, at least one recess. A method of manufacturing the structure includes: (a) providing a template comprising at least one recess having a recess depth; (b) providing an electrically conductive material in the at least one recess; and (c) removing part of the template to decrease the recess depth of the at least one recess, thereby forming said protruding at least one electrically conductive element.Type: GrantFiled: April 23, 2013Date of Patent: August 9, 2016Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin Dooley, Richard Coull, Graeme Scott, Lorraine Byrne
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Publication number: 20160104675Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.Type: ApplicationFiled: January 29, 2013Publication date: April 14, 2016Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
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Patent number: 8575025Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.Type: GrantFiled: July 28, 2011Date of Patent: November 5, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: David Fitzpatrick, Kevin Dooley, Lorraine Byrne
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Publication number: 20130195140Abstract: The present invention relates to a temperature sensor comprising a network of carbon nanotubes, wherein an electrical resistance of the network of carbon nanotubes is indicative of a temperature to which the network of carbon nanotubes has been exposed. The present invention further relates to a time temperature indicator and a method of manufacturing a temperature sensor.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Inventors: Vittorio Scardaci, Graeme Scott, Richard Coull, Lorraine Byrne, Jonathan Coleman
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Publication number: 20130187670Abstract: Apparatus and methods related to capacitive sensors are provided. Metal walls are formed in an interdigitated pattern. A dielectric material corresponding to a selected analyte is deposited in contact with the metal walls thus defining a capacitive sensor. Exposure to the analyte causes the electrical capacitance to vary in accordance with intensity. Analyte detection or measurement, data acquisition, or other operations can be performed by way of the capacitive sensors of the present teachings.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Inventors: Kevin Dooley, Lorraine Byrne, Graeme Scott, Vladek Kasperchik
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Patent number: 8393077Abstract: A method for fabrication of passive electronic components includes disposing a sacrificial layer on a carrier and forming a curable resin layer on top of the sacrificial layer and patterning the curable resin to form a cured resin template having multiple pattern levels. A metal material is deposited into the first pattern level to form a first structure. A dielectric material is then formed on exposed portions of the first structure. A nonselective subtractive process is used to expose the sacrificial layer in a bottom of the second pattern level and metal material is deposited into the second pattern level and built up to include a portion which crosses over the dielectric material.Type: GrantFiled: September 15, 2009Date of Patent: March 12, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Lorraine Byrne, Kevin Dooley, David Fitzpatrick
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Publication number: 20130029481Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Inventors: David Fitzpatrick, Kevin Dooley, Lorraine Byrne
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Publication number: 20120219702Abstract: A film can be patterned with a nanomaterial. Such patterning can, in various embodiments, be performed by applying a uniform mixture of a solute in a solvent to a surface of the film to form a coating of a soluble material on the surface of the film in a pre-defined pattern that defines coated parts of the film and uncoated parts of the film, depositing an aqueous dispersion, including the nanomaterial and a surfactant, on the defined coated and uncoated parts of the film, washing the film to remove the coating of the soluble material and the nanomaterial from the defined coated parts of the film, but not removing the nanomaterial from the defined uncoated parts of the film, along with removing the surfactant from the defined coated and uncoated parts of the film, and leaving a pattern of the nanomaterial on the defined uncoated parts of the film.Type: ApplicationFiled: February 24, 2011Publication date: August 30, 2012Inventors: Graeme Scott, Lorraine Byrne, Richard Coull, Vittorio Scardaci
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Publication number: 20110063776Abstract: A method for fabrication of passive electronic components includes disposing a sacrificial layer on a carrier and forming a curable resin layer on top of the sacrificial layer and patterning the curable resin to form a cured resin template having multiple pattern levels. A metal material is deposited into the first pattern level to form a first structure. A dielectric material is then formed on exposed portions of the first structure. A nonselective subtractive process is used to expose the sacrificial layer in a bottom of the second pattern level and metal material is deposited into the second pattern level and built up to include a portion which crosses over the dielectric material.Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Lorraine Byrne, Kevin Dooley, David Fitzpatrick
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Patent number: 7737006Abstract: A method of manufacturing an electronic component comprising at least one n- or p-doped portion, comprising the steps of: co-depositing inorganic semi-conducting nanoparticles and dopant on a substrate, the nanoparticles being a group four element such as silicon or germanium; fusing the nanoparticles by heating to form a continuous layer; and subsequently; and, recrystallising the layer.Type: GrantFiled: October 30, 2003Date of Patent: June 15, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Paul Colfer, Lorraine Byrne, Eugene Cahill, Phil Keenan, Niall Stobie
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Publication number: 20060237719Abstract: A method of manufacturing an electronic component comprising at least one n- or p-doped portion, comprising the steps of: co-depositing inorganic semi-conducting nanoparticles and dopant on a substrate, the nanoparticles being a group four element such as silicon or germanium; fusing the nanoparticles by heating to form a continuous layer; and subsequently; and, recrystallising the layer.Type: ApplicationFiled: October 30, 2003Publication date: October 26, 2006Inventors: Paul Colfer, Lorraine Byrne, Eugene Cahill, Phil Keenan, Niall Stobie
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Publication number: 20060214577Abstract: A layer of a material is deposited onto a substrate of an electroluminescent lamp in accordance with a desired image. An action is performed to the material to render the material at least partially tacky. Electroluminescent powder is deposited onto the substrate. The electroluminescent powder adheres to the substrate where the material has been deposited thereon.Type: ApplicationFiled: March 26, 2005Publication date: September 28, 2006Inventors: Lorraine Byrne, Philip Keenan, Anna Fenelon