Abstract: A collector contact (6) is fabricated which is attached on the side to the collector zone (1), and around which a moat (3) is produced which laterally restricts the collector zone (1). The depth of the moat (3) is so dimensioned to be at least equal to the vertical thickness of the collector zone (1). The collector contact (6) comprises a polycrystalline silicon layer which contains dopants of the same conductivity type as the collector zone (1), and covers a highly doped contacting zone (7') which has been diffused from the adjoining collector contact (6).

Abstract: In fabricating the contact, the electrode layer of polycrystalline silicon whose rim portion is bonded via a layer portion of insulating material to the substrate, is used at least throughout the length of a part of its rim portion for the lateral delimitation of a etching process, as an etch mask, in the course of which a frame-shaped layer portion is formed underneath the rim portion of the electrode layer, and the contact area of the substrate as bordering on the layer portion is exposed. Following the deposition of a metal layer of a metal forming a silicide in a thickness smaller than the thickness of the layer portion, and the heating for forming the silicide, the metal which has so far not reacted with the silicon, is removed by using an etching agent selectively dissolving the metal.

Abstract: In this method, said emitter area (6) and said collector area of a bipolar transistor are each covered with a portion (71, 72) of an oxidation mask layer in a conventional manner. After implantation of ions of said conductivity type of said base region, an oxide stripe (21) surrounding said emitter are (6) is formed by thermal oxidation. After removal of said portions (71, 72) of said oxidation mask layer, successive layers (9, 10) are deposited which consist at least of a top layer (10) and an underlying doped silicide layer (9). Using a masked anisotropic etching process through said oxide stripe (21), said successive layers (9, 10) are divided into said emitter electrode (61) and said collector electrode (32), out of which said emitter region (4) and said collector contact region (31) are diffused.

Abstract: The invention includes a method of manufacture of monolithic integrated VLSI circuits comprising bipolar transistors whose base regions are contacted in a self-aligned manner in proximity to the respective emitter regions by the use of silicide layers. The invention starts out from a process which, when using an insulating masking layer portion covering up the emitter area of the planar transistor, permits the self-aligned fabrication of emitter regions extending to the adjoining base region and to the base contacting region. Further embodiments of the process according to the invention permit the simultaneous manufacture of co-integrated CMOS circuits and of polycrystalline. Si-conductor leads whose resistances are reduced owing to the use of silicide layers.

Abstract: A method of producing an integrated insulated-gate field-effect transistor with an increased breakdown voltage provides in that at least one of the two zones, i.e. the source zone and/or the drain zone is surrounded by a relatively high-ohmic partial zone. This partial zone or the partial zones are first produced by way of ion implantation with the aid of a first implantation mask. After removal of this mask, the entire area of the field-effect transistor is covered with an oxidation masking layer comprising several selectively etchable partial layers, of which the lower partial layer is finally exposed and serves as the gate insulating layer. With the aid of the photoresist mask serving as an etching mask, openings are etched through the oxidation masking layer. The photoresist mask, together with the portions of the oxidation masking layer remaining therebelow, is used as an ion implantation mask for manufacturing both the source zone and the drain zone.

Abstract: In the process according to the invention, in addition to the conventional two photoresist processes for opening the contact holes and for manufacturing the interconnecting pattern, two photoresist processes are used with one photoresist mask each for manufacturing the regions of the planar transistor. Without additional photoresist masks, further semiconductor components, such as integrated resistors and/or lateral transistors are capable of being manufactured. The process is characterized by the fact that, the first photoresist mask is used to manufacture a diffusion masking layer which leaves the base area of the planar transistor unmasked. In this area, the dopings of the collector region are introduced into the substrate and the collector region is diffused. Thereafter, at a relatively small dose rate, there is carried out an implantation of dopings of the base region.

Abstract: A method of manufacturing bipolar transistors is described. The emitter areas are protected by means of an oxidation masking layer and subsequently after applying a photo-resist layer which defines the base areas two implantation processes of ions of the base zone conductivity type are performed. The one is performed with low doping dose and high acceleration voltage sufficient to render the masking layer penetrable and the other with high doping dose and low acceleration voltage as to render the masking layer impenetrable.

Abstract: The invention proposes a process for manufacturing a monolithic integrated circuit comprising at least one bipolar transistor in which the dopings of the regions are inserted into the substrate (2) exclusively by way of ion implantations. The invention deals with the problem of the current gain value variations during mass-production. This problem is solved in that during the implantation of the base dopings, in which the base area (32) is defined by means of a photoresist mask (5), the emitter area (11) is covered with an oxidation masking layer portion (71), with the ions of the base region (3) being implanted into the substrate surface once at a low accelerating energy and a great dose, with the oxidation masking layer portion (71) serving as the mask and, the next time, at a high accelerating energy and a relatively small dose, in the course of which the oxidation masking layer portion (1) is penetrated.

Abstract: This invention relates to a monolithically integrated threshold switch which switches on at an upper voltage value of a hysteretic characteristic and switches off at a lower voltage value especially adapted to I.sup.2 L ICs. Over a resistance the value of which determines the upper voltage value the input is fed to the base of a first transistor which has no injector nor current feeding, and to a first collector of a multicollector transistor the base of which is fed to its second collector and to a current source. Any output signal may be derived from any additional collector of one of the two transistors.

Abstract: This relates to a method of producing a monolithic integrated I.sup.2 L circuit including a bipolar analog circuit part. In order to realize good current gain values in the I.sup.2 L transistors as well as high collector breakdown voltages in the analog circuit part, the base zone of the analog circuit part is prediffused prior to diffusion of the I.sup.2 L base and injector regions. After such prediffusion, excessive doping material from the diffusion masking layer is removed and simultaneously windows in the diffusion mask over the I.sup.2 L base and injector regions are opened. Next, doping material having a lower concentration than that which was used for the prediffusion of the analog base region is prediffused into the exposed regions of the substrate. This results in an expanded prediffused base region in the analog circuit part.

Abstract: A device for scanning optical images wherein light intensity of a scanned image line is converted to a pulse width modulation rather than a charge profile. A photo transistor row is connected to an inverter chain, and OR-gates have outputs which are fed to a common read line while the input signal of each OR-gate is tapped over coordinated partial rows of the photo transistor row.