Abstract: The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model within a register transfer level, providing a filtering algorithm or filtering rules for signals occurring in the HDL or VHDL hardware description model, extracting signals from the HDL or VHDL hardware description model according to said filtering algorithm or filtering rules in order to get relevant signals, performing a simulation process of the HDL or VHDL hardware description model, performing a checking routine for the relevant signals in every cycle and storing and/or cumulating the relevant signals in a data base. Further the present invention relates to a corresponding system.

Abstract: A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).

Abstract: The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.

Abstract: A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).

Abstract: The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.

Abstract: The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model (10) within a register transfer level, providing a filtering algorithm or filtering rules (12) for signals occurring in the HDL or VHDL hardware description model (10), extracting signals from the HDL or VHDL hardware description model (10) according to said filtering algorithm or filtering rules (12) in order to get relevant signals, performing a simulation process (18) of the HDL or VHDL hardware description model (10), performing a checking routine (20) for the relevant signals in every cycle and storing and/or cumulating the relevant signals in a data base (22). Further the present invention relates to a corresponding system.