Abstract: In a reactor for gasification of solid carbonaceous materials in a fluidized bed under elevated pressure and at high temperatures using a hot gasification agent, a feed device for the gasification agent is installed in the lower part of the reactor chamber and traverses this chamber in the form of a bridge, which has an arch joined to the walls of the reactor chamber, said arch consisting of refractory brick and supporting a section of metal pipe. The latter is shielded from the outside by the arch and by a top-mounted structure of refractory material. On the inside, the metal pipe is also provided with a tubular lining of refractory material. Metal pipe, lining, and arch have openings for passage of the gasification agent. The size and shape of the openings are selected to assure passage of the gasification agent even if the parts undergo changes in length as a result of the effects of temperature.

Abstract: Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of the semiconductor memory with the exception of one selected word line are at a low level. The circuit arrangement also has an inactive power-down mode of operation, wherein all word lines at a high level. Both of the modes of operation are represented by a signal having a first level for the active mode of operation and a second level for the inactive mode of operation.

Abstract: Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, including current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller than the cut-off voltage of the respective selection transistors.

Abstract: A field effect transistor having an extremely short channel length in which a doped semiconductor layer of one conductivity type has oppositely doped source and drain zones in a surface side thereof. A first gate electrode is separated from the semiconductor layer surface by an insulating layer. The first gate electrode covers the region between the source and drain zones with the exception of a strip-like semiconductor region directly adjoining the source zone. A second gate electrode is provided above the strip-like semiconductor region and is insulated from the first gate electrode by a second insulating layer. The first gate electrode is connected to a bias voltage source and the second gate electrode is arranged to be connected to a control voltage.

Abstract: An insulated gate field effect transistor has a channel region in a doped semiconductor substrate covered by a thin film region of the insulating layer and has borders defined by thick film regions disposed parallel to the source-drain direction. The transistor further includes a pair of narrow strip zones in the region of the channel borders also running parallel to the source-drain direction which are doped weaker than and oppositely to the substrate doping to partially compensate the substrate doping and in transistors of the depletion type can overcompensate the substrate doping. The compensation provided by the strip zones decreases the substrate control effect so that the effective channel width of the transistor is less susceptible to fluctuations in operating voltages.

Abstract: A field effect transistor having an extremely short channel length in which a semiconductor substrate of one conductivity type has source and drain zones of the opposite conductivity type. A first gate electrode is separated from the substrate surface by a first insulating layer. The substrate has a surface side counter zone doping extending between the source and drain with the exception of a narrow strip-like zone which directly adjoins the source. The strip-like zone and at least an adjoining part of the surface side counter doped zone is covered by the first gate electrode. A second insulating layer is formed on the first gate electrode and on the drain side edge face of the first gate electrode. A coating on the second insulating layer covering that portion of the first insulating layer not covered by the first gate electrode is formed. The source side edge of the coating determines the drain side boundary of the strip-like zone.