Patents by Inventor Lou Hutter

Lou Hutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EEPROM with reduced manufacturing complexity
    Publication number: 20040175891
    Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).
    Type: Application
    Filed: March 15, 2004
    Publication date: September 9, 2004
    Applicant: Texas Instruments Deutschland GmbH
    Inventors: Jozef C. Mitros, Imran Khan, William Nehrer, Lou Hutter, Dirk Preikszat
  • EEPROM with reduced manufacturing complexity
    Patent number: 6734491
    Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Jozef C. Mitros, Imran Khan, William Nehrer, Lou Hutter, Dirk Preikszat