Patents by Inventor Loubna Hannati

Loubna Hannati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Design-for-test apparatuses and techniques
    Patent number: 9595316
    Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include an SRAM cell, read/write (R/W) circuitry to provide a nominal word line (WL) voltage and a nominal BL voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 14, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot
  • DESIGN-FOR-TEST APPARATUSES AND TECHNIQUES
    Publication number: 20160078927
    Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include an SRAM cell, read/write (R/W) circuitry to provide a nominal word line (WL) voltage and a nominal BL voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Applicant: INTEL IP CORPORATION
    Inventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot
  • For-test apparatuses and techniques
    Patent number: 9236144
    Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell, read/write/decoder (R/W/decoder) circuitry to provide a nominal word line (WL) voltage and a nominal bit line (BL) voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 12, 2016
    Assignee: INTEL IP CORPORATION
    Inventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot
  • DESIGN-FOR-TEST APPARATUSES AND TECHNIQUES
    Publication number: 20150262707
    Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell, read/write/decoder (R/W/decoder) circuitry to provide a nominal word line (WL) voltage and a nominal bit line (BL) voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Inventors: Vianney Choserot, Loubna Hannati, Nabil Badereddine, Christophe Chanussot