Abstract: A method and system for identifying a defocus wafer by mapping a topography of each wafer in a first wafer batch using a level sensor apparatus (100); calculating a focus spot deviation (402) from the data, the focus spot deviation (402) corresponding to a height by which a focus spot of a photo exposure module would be defocused by the topography; converting the focus spot deviation (402) to a corresponding wafer stage set point to which the photo exposure module is set, to focus the focus spot on each wafer in the wafer batch; and identifying a defocus wafer in the wafer batch, as a wafer having a topography that would defocus the focus spot, even when the photo exposure module is set to the wafer stage set point.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: In a container for transporting a reticle during a semiconductor manufacturing process, the reticle including a base made of isolating material and a metallic layer deposited onto a surface of the base, disclosed is a method for isolating and removing environmental contaminants which includes filling the container with inert gas, thereby purging the environmental contaminants, as well as inlet and outlet features to allow for the purging of clean inert gas and impurities.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: A novel method and apparatus for reducing or eliminating electrostatic charging of wafers during a spin-dry step of wafer cleaning is disclosed. The method includes rinsing a wafer, typically by dispensing a cleaning liquid such as deionized water on the wafer while spinning the wafer; and spin-drying the wafer by sequentially rotating the wafer in opposite directions. The apparatus includes a wafer support platform that is capable of sequentially rotating a wafer in opposite directions to spin-dry the wafer.

Abstract: An improved method of wafer height mapping using a wafer level sensor eliminates or substantially minimizes the “spacing” in the wafer height mapping data usually caused by having an exposure field on a wafer whose width is less than the width of the measurement spot array of the wafer level sensor and also not being a multiple of the width of a single measurement spot. According to the improved method, the measurement spot array is first translated towards one edge of the exposure field and scanned. Then the measurement spot array is translated towards the other edge of the exposure field and scanned second time to map the area that was missed during the first mapping scan.

Abstract: An improved method of wafer height mapping using a wafer level sensor eliminates or substantially minimizes the “spacing” in the wafer height mapping data usually caused by having an exposure field on a wafer whose width is less than the width of the measurement spot array of the wafer level sensor and also not being a multiple of the width of a single measurement spot. According to the improved method, the measurement spot array is first translated towards one edge of the exposure field and scanned. Then the measurement spot array is translated towards the other edge of the exposure field and scanned second time to map the area that was missed during the first mapping scan.

Abstract: An improved photo resist coating and developing system comprising a track unit and a scanner unit is disclosed. The track unit has a coating unit for coating photo resist on a wafer. The scanner unit includes an enhanced wafer pre-alignment module, an expose stage, and a develop module. The enhanced wafer pre-alignment module is capable of performing wafer edge exposure (WEE) which conventionally required a separate WEE module as part of the track unit. By incorporating the WEE function into the wafer pre-alignment module of the scanner unit, the WEE module of the track unit is no longer required and duplication of wafer alignment and centering performed by the WEE module is eliminated.

Abstract: A method and system is disclosed for reducing and monitoring precipitated defects on mask reticles. A predetermined gas is provided into an environment surrounding the reticle assembly for reducing a formation of the precipitated defects around the mask reticle caused by photolithography under a light source having a small wavelength.

Abstract: A method and system for identifying a defocus wafer by mapping a topography of each wafer in a first wafer batch using a level sensor apparatus (100); calculating a focus spot deviation (402) from the data, the focus spot deviation (402) corresponding to a height by which a focus spot of a photo exposure module would be defocused by the topography; converting the focus spot deviation (402) to a corresponding wafer stage set point to which the photo exposure module is set, to focus the focus spot on each wafer in the wafer batch; and identifying a defocus wafer in the wafer batch, as a wafer having a topography that would defocus the focus spot, even when the photo exposure module is set to the wafer stage set point.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.