Abstract: The method and apparatus described herein uses modern digital logic that is used to meet the need by controlling Switch-Mode Power System (SMPS) components to produce efficient conversion of the AC input source to a DC output load, maintain a near-unity Power Factor Control (PFC), require relatively small components for energy storage and filtering, as well as support a form of soft-start load application to a Poly-Phase AC source.

Abstract: A micro-electro-mechanical (MEMS) exhaust valve-based impact attenuating fluid filled cell for use in cushioning impact and decelerating of a wearer's body portion (e.g. head, shoulder, torso, etc.) after an impact. In combination with the use of accelerometers, pressure sensors, location and other electronics supply signals to a microcontroller, the controlled opening/closing of said exhaust valve (resulting in the expelling of said fluids with an optional combination with cell refill means) when certain parameters exceed a threshold.

Abstract: A micro-electro-mechanical (MEMS) exhaust valve-based impact attenuating fluid filled cell for use in cushioning impact and decelerating of a wearer's body portion (e.g. head, shoulder, torso, etc.) after an impact. In combination with the use of accelerometers, pressure sensors, location and other electronics supply signals to a microcontroller, the controlled opening/closing of said exhaust valve (resulting in the expelling of said fluids with an optional combination with cell refill means) when certain parameters exceed a threshold.

Abstract: A micro-electro-mechanical (MEMS) exhaust valve-based impact attenuating fluid filled cell for use in cushioning impact and decelerating of a wearer's body portion (e.g. head, shoulder, torso, etc.) after an impact. In combination with the use of accelerometers, pressure sensors, location and other electronics supply signals to a microcontroller, the controlled opening/closing of said exhaust valve (resulting in the expelling of said fluids with an optional combination with cell refill means) when certain parameters exceed a threshold.

Abstract: Embodiments may include a method, system and apparatus for providing a reference voltage supply. A series resistor is provided between a power supply and a bandgap circuit coupled to an amplifier. A shunt transistor circuit is operatively coupled to the series resistor. A programmable output voltage is provided based upon the shunt transistor circuit and a first value of the series resistor.

Abstract: Embodiments may include a method, system and apparatus for providing a reference voltage supply. A series resistor is provided between a power supply and a bandgap circuit coupled to an amplifier. A shunt transistor circuit is operatively coupled to the series resistor. A programmable output voltage is provided based upon the shunt transistor circuit and a first value of the series resistor.

Abstract: Fiber optic assemblies include subunit cables wrapped in binders. The assemblies have small cross sections and low bend radii while maintaining acceptable attenuation losses. SZ stranding of the subunit cables allows ease of access to the individual cables during installation.

Abstract: Fiber optic assemblies include subunit cables wrapped in binders. The assemblies have small cross sections and low bend radii while maintaining acceptable attenuation losses. SZ stranding of the subunit cables allows ease of access to the individual cables during installation.

Abstract: A transmission line (218) is formed to have a characteristic impedance which increases at a first substantially exponential rate with respect to a distance from the input (202). A plurality of resonators (206-214) are coupled to the transmission line and positioned at a plurality of locations along the transmission line. The plurality of resonators has resonant frequencies that decrease at a second substantially exponential rate with respect to the distance from the input. An output signal (810, 812) is obtained at a point in the filter that produces a filter response having a corner frequency.

Abstract: A fiber optic cable having at least two interfaces being formed by first and second members. Between the interfaces is at least one retention area having an optical fiber component disposed therein. The retention area is disposed generally longitudinally and non-helically relative to an axis of the cable. The cable may also include a cable jacket substantially surrounding the members, a cushioning zone adjacent the optical fiber component, a water-blocking component and/or an interfacial layer. In another embodiment, a fiber optic cable includes a strength group having at least one strength member and an optical fiber being proof-tested to 125 KPSI or greater.

Abstract: A transmission line (218) is formed to have a characteristic impedance which increases at a first substantially exponential rate with respect to a distance from the input (202). A plurality of resonators (206-214) are coupled to the transmission line and positioned at a plurality of locations along the transmission line. The plurality of resonators has resonant frequencies that decrease at a second substantially exponential rate with respect to the distance from the input. An output signal (810, 812) is obtained at a point in the filter that produces a filter response having a corner frequency.

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A fiber optic cable having at least two interfaces being formed by first and second members. Between the interfaces is at least one retention area having an optical fiber component disposed therein. The retention area is disposed generally longitudinally and non-helically relative to an axis of the cable. The cable may also include a cable jacket substantially surrounding the members, a cushioning zone adjacent the optical fiber component, a water-blocking component and/or an interfacial layer. In another embodiment, a fiber optic cable includes a strength group having at least one strength member and an optical fiber being proof-tested to 125 KPSI or greater.

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A selective call receiver (500) includes a radio receiver (501) and a processor (508). The radio receiver includes an antenna (502), a combination circuit (204), a bandpass filter (208), mixers (212, 214), analog-to-digital converters (222, 224), digital mixers (234, 236), a second combination circuit (242), and a digital-to-analog converter (246). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.

Abstract: A random number generator includes a sample clock having a sample clock rate, a chaotic oscillator having a characteristic upper frequency, and an output section. The chaotic oscillator includes a quantized linear section and a non-linear section. The quantized linear section includes multiple quantized integrators coupled to the sample clock and intercoupled in a linear intercoupling. The non-linear section is coupled in a feedback manner with the quantized linear section. The output section generates a random binary output signal having the sample clock rate, formed by a logical combination of binary signals, of which one binary signal is generated by each of the multiple quantized integrators. Each quantized integrator includes an analog to digital converter that preferably includes a sigma delta converter that generates one of the binary signals.

Abstract: A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.

Abstract: A composite cable for use in indoor or indoor/outdoor applications having a fiber optic core section includes at least one optical fiber. The composite cable includes a conductor and water blocking section, the conductor and water blocking section having a set of conductors providing mechanical strength and flame inhibiting characteristics to the composite cable. At least one interstice of the composite cable includes a water blocking member therein. An armor layer surrounds the conductor and water blocking section, and the armor layer is surrounded by a cable jacket with an interfacial zone defined therebetween. The interfacial zone includes a controlled bond layer so that during flame tests, as the jacket burns and forms a char barrier around the tape layer, the controlled bond layer supports the char barrier relative to the armor tape, thereby protecting the tape from flames and inhibiting the propagation of flame along the cable.

Abstract: A composite cable (10) includes a core section (12), a tensile strength section (20), a conductor and water blocking section (30), an armor tape (50), and an outer jacket (60). Core section (12) includes at least one fiber optic conductor (14), and conductor and water blocking section (30) includes twisted pair conductors (32) and water blocking members (36,37). Tensile strength section (20) includes strength members (22). Composite cable (10) combines the high bit-rate capacity of fiber optic conductor (14) with the electrical signal/power carrying capacity of electrical conductors (32) and meets water blocking and tensile strength requirements.

Abstract: A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.