Abstract: A data processing system which includes a host processor and an input/output (I/O) controller unit for controlling communication with I/O devices. The I/O controller unit responds to a plurality of I/O commands from the host processor each of which is associated with one of a plurality of control block lists each containing one or more control commands. The I/O controller unit can access and store control commands from each of the plurality of control block lists and execute the stored commands from such lists in a selected order for providing the most effective execution thereof.

Abstract: A data processing system which includes a host processor and an input/output (I/O) controller unit for controlling communication with I/O devices. The controller processor receives I/O commands from the host processor, accesses and stores control block lists of control commands associated with such I/O commands, and executes the control commands from such control block lists. The controller unit stores controller information concerning the operational capability of the controller unit and the host processor is capable of accessing such controller information and in turn can modify such operational capability if desired.

Abstract: An apparatus provides a sequence detected signal indicating that a synchronization sequence occurring at regular intervals in a stream of data has occurred or should have occurred. The apparatus includes logic for detecting the synchronization sequence, logic responsive to the detection logic for producing the sequence detected signal when the detection logic detects the sequence, and logic for producing the sequence detected signal at a fixed time after the synchronization sequence should have occurred. If the synchronization sequence did occur, the apparatus thus produces two sequence detected signals; however, the device receiving the sequence detected signal responds to the first sequence detected signal and ignores the second. If the synchronization sequence did not occur, the device receiving the sequence detected signal responds to the sequence detected signal produced by the logic responsive to the timing apparatus.

Abstract: Logic circuitry for use in electrical apparatus for providing an interrupt signal to a controller when there is a power failure in the electrical apparatus. The logic circuitry is connected to a bus from the controller. When the logic circuitry receives a power failure signal, it sets an interrupt state register and provides an interrupt signal on the bus as long as the interrupt state register is set. If the power failure signal no longer indicates a power failure, the logic circuitry responds to a signal from the controller indicating that the interrupt has been received by resetting the interrupt state register, thereby ending the interrupt. However, if the power failure signal is still active, the logic circuitry will not reset the interrupt state register in response to the signal from the controller.

Abstract: A method useful in a disk drive for diagnosing malfunctions in the path by which data codes are encoded into disk codes and written to the disk and by which disk codes are read from the disk and decoded into data codes. The disk drive in which the method is used includes control apparatus having a memory for controlling operation of the disk drive, a read-write processor for translating data codes to disk codes and vice-versa, and data transfer means including a memory for transferring data codes internally in the disk drive. In the method, a copy of a test pattern stored in the memory belonging to the control apparatus is made and provided to the memory in the data transfer means. It is provided from then to the read-write processor, which translates the data codes in the copy to disk codes and writes them to a diagnostic track on the disk. The disk codes are then read from the diagnostic track and translated by the read-write processor.

Abstract: A digital data bus system for connecting a controller and a disk drive. Data on the disk is stored in track sectors containing a header and data. The controller includes a high-speed processor which performs a header compare operation comparing the values received from a header with the expected contents of the header and operations which determine when all of the data in a track sector has been transferred. The digital data bus system includes a bus for transferring data between the controller and the disk drive and a header-data mode bus for providing a header mode signal and a data mode signal from the controller to the disk drive. During an operation transferring data between the controller and the disk, the disk drive responds to the header mode signal by transferring a header to the controller.

Abstract: Apparatus in a disk drive connected by separate buses to two controllers for suspending the effect of a reserve instruction received from one controller when the other controller has already reserved the disk drive until the other controller releases the disk drive. The apparatus corresponding to each controller consists of suspended reserve logic and a register for retaining state indicating whether the controller has reserved the bus and state indicating whether the reserve operation has been suspended for the controller. The suspended reserve logic for a given controller receives inputs from the controller's bus, from the state stored in its register, and from the state in the suspended reserve apparatus for the other controller indicating whether that controller has reserved the disk drive. Outputs from the suspended reserve logic go to its register.

Abstract: Error detection circuitry for use in a data processing system which utilizes a programmable logic array for controlling, during a write operating mode, the generation of a write error word by an error register, which write error word is thereupon stored together with the associated data words in a data storage device and for controlling, during a read operating mode, the generation of a read error word, the error register thereupon effectively comparing the read error word with the originally stored write error word to produce a remainder word when an error is present.