Abstract: A multi-purpose direct memory access packet control system for moving packets within a multi-processor computer system. The data memory is allocated into a number of unique data spaces suitable for storage of packets. Each data space is controlled by a unique type of buffer manager. Different buffer formats such as circular, linear, and offset are provided without the intervention of the processor and its associate software. Data packets are rapidly transmitted from an input buffer to the appropriate section of the memory and vice versa.

Abstract: An arrangement for automatic replacement of faulty memory elements in a M-row by N-column memory array provides increased memory reliability. The memory array is coupled to a computer by a group of transceivers. Replacement memory elements are provided in a column replacement fashion and are selectively enabled on a row-by-row basis for detected faults within the memory elements of the memory array. Transceivers are appropriately enabled to select one of two memory elements for each column. For a detected fault in a memory element, each memory element is shifted to an adjacent memory element and the replacement memory element is employed to substituted for the last regular memory element.

Abstract: A method and apparatus for switching data between a selected pair of data processing elements. The method involves steps of sending a first service request signal from a first data processing element to a switch, where the first service request signal includes a first destination, sending a first data message to the switch and storing the first service request signal and the first data message at least temporarily in a first buffer memory. The method further involves steps of routing the first data message to the first destination and initiating communication between the first data processing element and the first destination.

Abstract: A memory system containing redundant portions for the achievement of high reliability is disclosed. A total of n memory elements are utilized, but only m of the n memory elements may be on-line at any one time. On-line and off-line status of each of the n memory elements is defined independently from all other memory elements. Parity or hamming code error detection data associated with an external data bus are changed to cyclical code error detection data for storage in the memory system.

Abstract: In a side looking radar, electronic timing circuits for dividing the radar beam into a plurality of groups of azimuth cells of equal size, the switching circuits being dependent upon the number of pulse repetition intervals per unit of travel to maintain the size of the azimuth cells in the different groups relatively constant. The apparatus also contains circuitry for scaling the output in each of the different azimuth groups.

Abstract: MAPS compressed image data is arranged symmetrically so that it can be stored in a substantially reduced memory and operated on for smoothing with substantially less components. A serial and a parallel design are disclosed, both of which have substantially reduced memories and a reduced number of stages for processing of the surround areas.

Abstract: A directional main antenna and N omnidirectional auxiliary antennas connected to each supply an m-sample batch of signals to apparatus for developing a weighting vector 2 through Batch Covariance Relaxation apparatus, which weighting vector is then used to weight the signals from the auxiliary antennas and the weighted outputs are summed with the signal from the main antenna to suppress undesired sidelobe interferences. The processor includes apparatus performing complex vector dot product multiplication, dividing apparatus, apparatus for adding or subtracting to provide the recursive updating of vectors and memories for storing the various signals between operations.