Abstract: An image processing system and method are described which use entropy values in processing the image. For each of a plurality of segments of an image, the segment is considered as a stream of bits and a bit difference is computed between pairs of sequential bit sequences in the stream of bits. An entropy value of the segment is computed as a function of the bit differences. The image is processing based on the computed entropy values, which may include compressing some or all of the image segments using an acceleration factor that is based on the computed entropy value for the segment. In this way, differences in entropy, which correlate with the compressibility of the image segment, can ensure an optimal compression of the segment, or in some cases, no compression.

Abstract: An image processing system and method are described which use entropy values in processing the image. For each of a plurality of segments of an image, the segment is considered as a stream of bits and a bit difference is computed between pairs of sequential bit sequences in the stream of bits. An entropy value of the segment is computed as a function of the bit differences. The image is processing based on the computed entropy values, which may include compressing some or all of the image segments using an acceleration factor that is based on the computed entropy value for the segment. In this way, differences in entropy, which correlate with the compressibility of the image segment, can ensure an optimal compression of the segment, or in some cases, no compression.

Abstract: What is disclosed is a system and method for increasing throughput in the image processing path of a digital document reproduction device. A digital image to be processed is received. Memory is allocated into two buffers, B[0] and B[1]. Each buffer has size S B ? M 2 , where M is a size of the allocation. The digital image is divided into N number of tiles. Then, for tiles Ti, where i=1 to N: (A) the image data of tile Ti is decompressed into buffer B[((i% 2)=0], and (B) the image data of buffer B[(i% 2)?0] is decompressed into the image path pipeline. Send a signal indicating that processing of the digital image has completed.

Abstract: What is disclosed is a system and method for increasing throughput in the image processing path of a digital document reproduction device. A digital image to be processed is received. Memory is allocated into two buffers, B[0] and B[1]. Each buffer has size S B ? M 2 , where M is a size of the allocation. The digital image is divided into N number of tiles. Then, for tiles Ti, where i=1 to N: (A) the image data of tile Ti is decompressed into buffer B[((i% 2)=0], and (B) the image data of buffer B[(i% 2)?0] is decompressed into the image path pipeline. Send a signal indicating that processing of the digital image has completed.

Abstract: A hardware interface usable to communicate with electrically erasable read-only memory devices and, optionally, other external controls or devices, includes self-monitoring power supply circuitry, an EEPROM driver and noise and signal degradation prevention circuitry, and optional input/output circuitry which provides for programmatically cycling power to the memory device. The self-monitoring power supply circuitry is capable of determining whether a power supply has reached the hardware interface. The EEPROM driver and noise and signal degradation prevention circuitry reduces signal noise and/or signal degradation and driver circuitry for programming, monitoring, and downloading information to and from the EEPROM devices. The digital input/output circuitry is capable of controlling the power supply to the hardware interface, downloading or monitoring information to the hardware interface, or controlling/responding to external devices or controls.

Abstract: A hardware interface usable to communicate with electrically erasable read-only memory devices and, optionally, other external controls or devices, includes self-monitoring power supply circuitry, an EEPROM driver and noise and signal degradation prevention circuitry, and optional input/output circuitry which provides for programmatically cycling power to the memory device. The self-monitoring power supply circuitry is capable of determining whether a power supply has reached the hardware interface. The EEPROM driver and noise and signal degradation prevention circuitry reduces signal noise and/or signal degradation and driver circuitry for programming, monitoring, and downloading information to and from the EEPROM devices. The digital input/output circuitry is capable of controlling the power supply to the hardware interface, downloading or monitoring information to the hardware interface, or controlling/responding to external devices or controls.