Patents by Inventor Louis Bennie Capps, Jr.

Louis Bennie Capps, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240187440
    Abstract: Systems and methods for providing resilience in network communications are provided that leverage novel switch device architectures. An example switch device for providing resilience in network communications includes a signal routing mechanism configured to selectively provide communication between at least one first network port and two of a plurality of second network ports. The signal routing mechanism receives an indication of a malfunction associated with one of the two of the plurality of second network ports and communicably connects the at least one first network port with the other of the two of the plurality of second network port. The first network ports may be positioned in a first array and each of the plurality of second network ports may be positioned in a second array.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 6, 2024
    Inventors: Ioannis (Giannis) Patronas, Paraskevas Bakopoulos, Nikolaos Argyris, Dimitrios Kalavrouziotis, Dimitrios Syrivelis, Elad Mentovich, Prethvi Ramesh Kashinkunti, Louis Bennie Capps, JR., Julie Irene Marcelle Bernauer, Eitan Zahavi
  • Publication number: 20240121158
    Abstract: Apparatuses, systems, and methods are provided for scalable networking systems. An example system includes a plurality of core switches and a first stage patch panel associated with operation of a first set of network ports. In an operational configuration in which the first stage patch panel is coupled with the plurality of core switches, the first stage patch panel is configured to operatively couple the first set of network ports and a first portion of the plurality of core switches such that signals may pass therebetween. Furthermore, the first stage patch panel may preclude communication to a remaining portion of the plurality of core switches. The system may include a second stage patch panel associated with a second set of network ports that is operatively coupled with the plurality of core switches in the absence of the first stage patch panel so as to scale the networking system.
    Type: Application
    Filed: November 10, 2022
    Publication date: April 11, 2024
    Inventors: Paraskevas Bakopoulos, Dimitrios Kalavrouziotis, Nikolaos Argyris, Ioannis (Giannis) Patronas, Elad Mentovich, Eitan Zahavi, Prethvi Ramesh Kashinkunti, Louis Bennie Capps, JR., Julie Irene Marcelle Bernauer, James Steven Fields, JR.
  • Publication number: 20240113943
    Abstract: Systems, computer program products, and methods are described herein for dynamic reconfiguration of network communications. An example system includes a first network pod including a first set of network ports, a second network pod including a second set of network ports, a set of network cores, and a first intermediate network switch. The first intermediate switch operatively couples the first network pod, the second network pod, and the set of network cores. The first intermediate network switch is configured to selectively establish full bisectional bandwidth data communication between a subset of the set of network cores, a subset of the first set of network ports, and a subset of the second set of network ports.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 4, 2024
    Applicant: Mellanox Technologies, Ltd.
    Inventors: Ioannis (Giannis) PATRONAS, Paraskevas BAKOPOULOS, Dimitrios SYRIVELIS, Elad MENTOVICH, Eitan ZAHAVI, Louis Bennie CAPPS, Jr., Prethvi Ramesh KASHINKUNTI, Julie Irene Marcelle BERNAUER, Nikolaos TERZENIDIS
  • Publication number: 20240098040
    Abstract: Systems, apparatuses, and methods are provided for resilience in network communications. An example system includes at least one first network port including a first plurality of subports and at least one second network port including a second plurality of subports. The system also includes an intermediate switch communicably connected to the at least one first network port and the at least one second network port. At least one of the first plurality of subports includes at least one first offline subport that is inoperable in an instance in which each of the remaining first plurality of subports are operable. The intermediate switch is configured to route communication from one of the second plurality of subports to the at least one first offline subport in an instance in which the intermediate switch receives an indication of a malfunction associated with the first plurality of subports.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 21, 2024
    Inventors: Ioannis (Giannis) Patronas, Paraskevas Bakopoulos, Dimitrios Syrivelis, Nikolaos Argyris, Elad Mentovich, Louis Bennie Capps, JR., Prethvi Ramesh Kashinkunti, Julie Irene Marcelle Bernauer, Eitan Zahavi
  • Publication number: 20240098039
    Abstract: Systems and methods for resilience in network communications are provided. An example system includes a first network port pair including a first input network port and a first output network port. The system further includes an intermediate switch configured to communicably connect the first input network port and the first output network port and a first redundant network port communicably connected with the intermediate switch. The intermediate switch establishes communication between the first input network port and the first redundant network port in an instance in which the intermediate switch receives an indication of a malfunction associated with the first output network port or establishes communication between the first output network port and the first redundant network port in an instance in which the intermediate switch receives an indication of a malfunction associated with the first input network port.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 21, 2024
    Inventors: Ioannis (Giannis) Patronas, Paraskevas Bakopoulos, Dimitrios Syrivelis, Nikolaos Argyris, Elad Mentovich, Louis Bennie Capps, JR., Prethvi Ramesh Kashinkunti, Julie Irene Marcelle Bernauer, Eitan Zahavi
  • Publication number: 20240039627
    Abstract: Systems, computer program products, and methods are described herein for network discovery, port identification, and/or identifying fiber link failures in an optical network, in accordance with an embodiment of the invention. The present invention may be configured to sequentially connect each port of an optical switch to a network port of a server and generate, based on information associated with network devices connected to the ports, a network map. The network map may identify which network devices are connected to which ports of the optical switch and may permit dynamic port mapping for network installation, upgrades, repairs, and/or the like. The present invention may also be configured to determine a fiber link in which a failure occurred and reconfigure the optical switch to allow communication between an optical time-domain reflectometer and the fiber link to test the fiber link.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 1, 2024
    Inventors: Paraskevas Bakopoulos, Konstantinos Tokas, Ioannis (Giannis) Patronas, Nikolaos Argyris, Dimitrios Syrivelis, Dimitrios Kalavrouziotis, Elad Mentovich, Eitan Zahavi, Louis Bennie Capps, JR., Prethvi Ramesh Kashinkunti, Julie Irene Marcelle Bernauer
  • Patent number: 9881099
    Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Danie M. Dreps, Luis A Lastras-Montano, Michael J Shapiro
  • Patent number: 8645673
    Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Thomas Edward Cook, Glenn G. Daves, Ronald Edward Newhart, Michael A. Paolini, Michael Jay Shapiro
  • Patent number: 8544006
    Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Michael A. Paolini, Michael Jay Shapiro
  • Patent number: 8495636
    Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Michael A. Paolini, Michael Jay Shapiro
  • Patent number: 8379847
    Abstract: Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Michael Jay Shapiro
  • Publication number: 20130013903
    Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Bell, JR., Louis Bennie Capps, JR., Thomas Edward Cook, Glenn G. Daves, Ronald Edward Newhart, Michael A. Paolini, Michael Jay Shapiro
  • Patent number: 8327126
    Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Thomas Edward Cook, Glenn G. Daves, Ronald Edward Newhart, Michael A. Paolini, Michael Jay Shapiro
  • Patent number: 8312455
    Abstract: A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Michael A. Paolini, Michael Jay Shapiro
  • Patent number: 8214660
    Abstract: A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Warren D. Dyckman, Michael Jay Shapiro
  • Publication number: 20110289270
    Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.
    Type: Application
    Filed: May 24, 2010
    Publication date: November 24, 2011
    Inventors: Robert H. Bell, JR., Louis Bennie Capps, JR., Daniel M. Dreps, Luis A. Lastras-Montano, Michael Jay Shapiro
  • Patent number: 7996693
    Abstract: A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Mark Elliott Hack, Steven Paul Hartman, Michael Jay Shapiro
  • Patent number: 7996346
    Abstract: A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Thomas Edward Cook, Thomas J. Dewkett, Naresh Nayar, Ronald Edward Newhart, Bernadette Ann Pierson, Michael Jay Shapiro
  • Patent number: 7930129
    Abstract: A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Anand Haridass, Ronald Edward Newhart, Michael J. Shapiro
  • Patent number: 7721119
    Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Warren D. Dyckman, Joanne Ferris, Anand Haridass, James Douglas Jordan, Ronald Edward Newhart, Michael Richard Ouellette, Michael Jay Shapiro