Patents by Inventor Louis Bernard Bushard
Louis Bernard Bushard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8117579Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.Type: GrantFiled: January 31, 2008Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: James Douglas Warnock, Wendel Dieter, David E. Lackey, William Vincent Huott, Leon Jacob Sigal, Louis Bernard Bushard, Sang Hoo Dhong
-
Patent number: 7844869Abstract: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.Type: GrantFiled: January 16, 2008Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Louis Bernard Bushard, Todd Alan Christensen, Jesse Daniel Smith
-
Patent number: 7733722Abstract: Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.Type: GrantFiled: January 12, 2009Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
-
Patent number: 7689950Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.Type: GrantFiled: October 16, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
-
Publication number: 20090199036Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: James D. Warnock, Wendel Dieter, David E. Lackey, William Vincent Huott, Leon Jacob Sigal, Louis Bernard Bushard, Sang Hoo Dhong
-
Publication number: 20090183044Abstract: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.Type: ApplicationFiled: January 16, 2008Publication date: July 16, 2009Inventors: Louis Bernard Bushard, Todd Alan Christensen, Jesse Daniel Smith
-
Publication number: 20090175106Abstract: Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.Type: ApplicationFiled: January 12, 2009Publication date: July 9, 2009Applicant: International Business Machines CorporationInventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
-
Publication number: 20090063921Abstract: A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in current that occur during logical built-in self testing (LBIST) operations in integrated circuits. The method includes executing a first logical built-in self test sequence for a first logic region within an integrated circuit, subsequently executing a second logical built-in self test sequence for a second logic region within the integrated circuit, wherein the second test sequence is offset from the first test sequence by one or more clock cycles.Type: ApplicationFiled: August 28, 2007Publication date: March 5, 2009Inventors: Anthony Gus Aipperspach, Louis Bernard Bushard, Dennis Thomas Cox
-
Patent number: 7489572Abstract: A method implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.Type: GrantFiled: January 12, 2007Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
-
Publication number: 20080250290Abstract: A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.Type: ApplicationFiled: June 13, 2008Publication date: October 9, 2008Applicant: International Business Machines CorporationInventors: Louis Bernard Bushard, Nathan Paul Chelstrom, Naoki Kiryu, David John Krolak
-
Patent number: 7406640Abstract: A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.Type: GrantFiled: March 31, 2006Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Louis Bernard Bushard, Nathan Paul Chelstrom, Naoki Kiryu, David John Krolak
-
Publication number: 20080170449Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
-
Publication number: 20080169843Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.Type: ApplicationFiled: October 16, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
-
Patent number: 7318182Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.Type: GrantFiled: December 2, 2004Date of Patent: January 8, 2008Assignee: International Business Machines CorporationInventors: Louis Bernard Bushard, Sang Hoo Dhong, Brian King Flachs, Osamu Takahashi, Michael Brian White