Patents by Inventor Louis C. Brousseau

Louis C. Brousseau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7208784
    Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes. At least one nanoparticle is provided on the projecting feature between the first and second electrodes.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: April 24, 2007
    Assignee: Quantum Logic Devices, Inc.
    Inventor: Louis C. Brousseau, III
  • Patent number: 6888665
    Abstract: A molecule is wired into an electronic circuit by attaching a metal nanoparticle to the molecule and then electrically connecting a metal nanoparticle to the electric circuit. The metal nanoparticle interconnects can bridge the gap between small molecules and conventional electric circuits. An optical second harmonic also may be generated by impinging optical radiation having a first frequency on an array of molecularly bridged metal nanoparticles, to generate optical energy at a second frequency that is twice the first frequency. Red to blue light conversion thereby may be provided.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: May 3, 2005
    Assignee: North Carolina State University
    Inventors: Daniel Feldheim, Louis C. Brousseau, III, James P. Novak
  • Patent number: 6784082
    Abstract: Single-electron transistors include first and second electrodes and an insulating layer between them on a substrate. The insulating layer has a thickness that defines a spacing between the first and second electrodes. At least one nanoparticle is provided on the insulating layer. Accordingly, a desired spacing between the first and second electrodes may be obtained without the need for high resolution photolithography. An electrically-gated single-electron transistor may be formed, wherein a gate electrode is provided on the at least nanoparticle opposite the insulating layer end. Alternatively, a chemically-gated single-electron transistor may be formed by providing an analyte-specific binding agent on a surface of the at least one nanoparticle. Arrays of single-electron transistors also may be formed on the substrate.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: August 31, 2004
    Assignee: North Carolina State University
    Inventor: Louis C. Brousseau, III
  • Publication number: 20040113144
    Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. At least one nanoparticle is provided on the projecting feature between the first and second electrodes. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes.
    Type: Application
    Filed: October 7, 2003
    Publication date: June 17, 2004
    Inventor: Louis C. Brousseau
  • Patent number: 6673717
    Abstract: Nanopores for single-electron devices may be used as templates for placing of a desired number of nanoparticles at a desired location in the devices. Nanopores may be fabricated by providing on a substrate spaced apart electrode regions, a spacer region therebetween, and a cover layer on the spaced apart electrode regions and on the spacer region. A wet etching solution is contacted to the cover-layer. At least one of the spaced apart electrode regions is energized, to selectively wet etch the cover layer adjacent the spacer region and define a nanopore in the cover layer adjacent the spacer region. At least one nanoparticle is placed in the nanopore. Accordingly, nanopores can be aligned to a buried spacer region.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: January 6, 2004
    Assignee: Quantum Logic Devices, Inc.
    Inventor: Louis C. Brousseau, III
  • Publication number: 20040002195
    Abstract: Nanopores for single-electron devices may be used as templates for placing of a desired number of nanoparticles at a desired location in the devices. Nanopores may be fabricated by providing on a substrate spaced apart electrode regions, a spacer region therebetween, and a cover layer on the spaced apart electrode regions and on the spacer region. A wet etching solution is contacted to the cover layer. At least one of the spaced apart electrode regions is energized, to selectively wet etch the cover layer adjacent the spacer region and define a nanopore in the cover layer adjacent the spacer region. At least one nanoparticle is placed in the nanopore. Accordingly, nanopores can be aligned to a buried spacer region.
    Type: Application
    Filed: June 26, 2002
    Publication date: January 1, 2004
    Inventor: Louis C. Brousseau
  • Patent number: 6653653
    Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. At least one nanoparticle is provided on the projecting feature between the first and second electrodes. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: November 25, 2003
    Assignee: Quantum Logic Devices, Inc.
    Inventor: Louis C. Brousseau, III
  • Publication number: 20030067668
    Abstract: A molecule is wired into an electronic circuit by attaching a metal nanoparticle to the molecule and then electrically connecting a metal nanoparticle to the electric circuit. The metal nanoparticle interconnects can bridge the gap between small molecules and conventional electric circuits. An optical second harmonic also may be generated by impinging optical radiation having a first frequency on an array of molecularly bridged metal nanoparticles, to generate optical energy at a second frequency that is twice the first frequency. Red to blue light conversion thereby may be provided.
    Type: Application
    Filed: August 9, 2002
    Publication date: April 10, 2003
    Inventors: Daniel Feldheim, Louis C. Brousseau, James P. Novak
  • Publication number: 20030025133
    Abstract: Single-electron transistors include first and second electrodes and an insulating layer between them on a substrate. The insulating layer has a thickness that defines a spacing between the first and second electrodes. At least one nanoparticle is provided on the insulating layer. Accordingly, a desired spacing between the first and second electrodes may be obtained without the need for high resolution photolithography. An electrically-gated single-electron transistor may be formed, wherein a gate electrode is provided on the at least nanoparticle opposite the insulating layer end. Alternatively, a chemically-gated single-electron transistor may be formed by providing an analyte-specific binding agent on a surface of the at least one nanoparticle. Arrays of single-electron transistors also may be formed on the substrate.
    Type: Application
    Filed: September 17, 2002
    Publication date: February 6, 2003
    Inventor: Louis C. Brousseau
  • Publication number: 20030012930
    Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. At least one nanoparticle is provided on the projecting feature between the first and second electrodes. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes.
    Type: Application
    Filed: July 13, 2001
    Publication date: January 16, 2003
    Inventor: Louis C. Brousseau
  • Patent number: 6483125
    Abstract: Single-electron transistors include first and second electrodes and an insulating layer between them on a substrate. The insulating layer has a thickness that defines a spacing between the first and second electrodes. At least one nanoparticle is provided on the insulating layer. Accordingly, a desired spacing between the first and second electrodes may be obtained without the need for high resolution photolithography. An electrically-gated single-electron transistor may be formed, wherein a gate electrode is provided on the at least nanoparticle opposite the insulating layer end. Alternatively, a chemically-gated single-electron transistor may be formed by providing an analyte-specific binding agent on a surface of the at least one nanoparticle. Arrays of single-electron transistors also may be formed on the substrate.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: November 19, 2002
    Assignee: North Carolina State University
    Inventor: Louis C. Brousseau, III