Patents by Inventor Louis Cameron Fisher
Louis Cameron Fisher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9424182Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: GrantFiled: November 17, 2014Date of Patent: August 23, 2016Assignee: Mobile Semiconductor CorporationInventors: Louis Cameron Fisher, Stephen V. R. Hellriegel, Mohammad S. Ahmadnia
-
Publication number: 20150074344Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Applicant: MOBILE SEMICONDUCTOR CORPORATIONInventors: Louis Cameron Fisher, Stephen V. R. Hellriegel, Mohammad S. Ahmadnia
-
Patent number: 8918618Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: GrantFiled: July 2, 2013Date of Patent: December 23, 2014Assignee: Mobile Semiconductor CorporationInventors: Louis Cameron Fisher, Stephen V. R. Hellriegel, Mohammad S. Ahmadnia
-
Publication number: 20140013039Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: ApplicationFiled: July 2, 2013Publication date: January 9, 2014Applicant: MOBILE SEMICONDUCTOR CORPORATIONInventors: Louis Cameron Fisher, Stephen V. R. Hellriegel, Mohammad S. Ahmadnia
-
Patent number: 8504793Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: GrantFiled: January 31, 2012Date of Patent: August 6, 2013Assignee: Mobile Semiconductor CorporationInventors: Louis Cameron Fisher, Stephen V. R. Hellriegel, Mohammad S. Ahmadnia
-
Publication number: 20120131269Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Applicant: MOBILE SEMICONDUCTOR CORPORATIONInventors: Louis Cameron Fisher, Stephen V.R. Hellriegel, Mohammad S. Ahmadnia
-
Patent number: 8135933Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: GrantFiled: January 10, 2008Date of Patent: March 13, 2012Assignee: Mobile Semiconductor CorporationInventors: Louis Cameron Fisher, Stephen V. R. Hellriegel, Mohammad S. Ahmadnia
-
Publication number: 20090024819Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: ApplicationFiled: January 10, 2008Publication date: January 22, 2009Applicant: MOBILE SEMICONDUCTOR CORPORATIONInventors: Louis Cameron Fisher, Stephen V.R. Hellriegel, Mohammad S. Ahmadnia
-
Patent number: 7149142Abstract: Various methods, apparatuses, and systems are described in which a volatile memory that includes a plurality of volatile memory cells as well as a voltage limiting component and a current limiting component. Power consumption in a standby mode is controlled. The voltage limiting component and the current limiting component couple between the volatile memory cells and the ground voltage potential. One or more rows of memory cells in the memory array are isolated from the ground voltage potential to control power consumption in the standby mode by having the current limiting component stop passing current in the standby mode. A floating ground voltage potential sensed by each memory cell when in the standby mode is controlled by configuring the voltage limiting component to conduct when the floating ground voltage potential is larger than a threshold voltage of the voltage limiting component in order to reduce leakage current but reliably maintain the stored contents of the volatile memory cell.Type: GrantFiled: May 28, 2004Date of Patent: December 12, 2006Assignee: Virage Logic CorporationInventors: Louis Cameron Fisher, Charles Jeremy Brumitt